LVDS and SLVS on XEM6310


#1

Hi,
is it really necessary to set the VCCO voltages to 2.5V to be able to use LVDS signals? Or would it also works to keep it like it is and use the LVDS_33 standard? I ran some tests using LVDS_33 and the output signals look ok as far as I can tell.

Also, we want to use SLVS inputs. The user manual says that it is possible to use externally applied input voltage thresholds. Would that also work for SLVS signals? According to Xilinx it is also possible to pull down the common voltage of a LVDS receiver to SLVS level (200 mV) simply using an external termination resistor (is it really that easy?).

Thanks in advance
Till


#2

Where do you see that LVDS requires 2.5V on the XEM6310? If the documentation for the board is incorrect somewhere it would be good to know so that it can be corrected.

SLVS hasn’t been specifically tested on these boards so we can’t really comment on how easy it is to use or how well it will perform, perhaps another user can shed some light if they have used it in the past.


#3

In “FPGA I/O BANK Voltages” in the manual it is mentioned that the VCCO voltages need to be changed to 2.5 V to be able to use differential I/Os, and also Xilinx usually refers to 2.5V for LVDS. I just wanted to be sure that 3.3 V won’t cause any issues.
However, I’ve done some more tests and LVDS_33 works fine as far as I can tell.

I also built a simple LVDS to SLVS converter, according to Altera’s MaxIO guide, on a breadboard and it looks like the LVDS receivers are tolerant enough to handle SLVS inputs when using external termination resistors, at least up to a certain frequency.


#4

The “FPGA I/O Bank Voltages” section on this page: https://docs.opalkelly.com/display/XEM6310/Expansion+Connectors mentions both LVDS_33 and LVDS_25 as available for the XEM6310. This mirrors the Xilinx documentation in UG381.

For Artix 7 designs LVDS_33 is no longer available so you must use 2.5V VCCO on a bank to use LVDS, but this does not apply to Spartan 6 designs.


#5

Thanks for the clarification. LVDS_33 not mentioned in XEM6310-UM.pdf (20160107) though. The “FPGA I/O Bank Voltages” section only mentions 2.5 V.