Looking for SSRAM verilog model


Thanks for setting up this forum space.

I am looking for a SSRAM verilog model for the GSI GS8322Z36-200V part or equivalent. As commented on to my question regarding DDR2 access, the access model for the SSRAM is much simpler, but would like the confidence that I am correctly designing the access to this component for:
*]pipeline read-modify-write
*]pileline read

Any suggestions on what keywords I could search on, or where I could find a reference model?


Have you tried looking on GSI’s website? They have models for all their parts:


Didn’t see this link when I was on the GSI site. Can I suggest you add this link to your XEM5010 UG documentation.



Minor comment:

I am currently in contact with the GSI apps team to find missing:
tapcontrol, inbsr, iobsr, oebsr

Also based on your description in the XEM5010, you’ve tied off a number of signals and/or ganged them together.

Do you have a SSRAM wrapper verilog module that reflects these changes you’ve made on your board?


Hello Peter–

The pins you’re referring to are TMS, TDI, TDO, and TCK on the device. These are the JTAG test port and are unconnected on the XEM5010.

The User’s Guide contains this note:

[QUOTE]The redundant chip enable pins of the SSRAM have been tied to enable, as appropriate. E2 is tied to +1.8VDD and E3 is tied to DGND. ZQ has been left as a no-connect. LBO is tied to DGND, enabling linear byte order operation. Finally, all four byte enables (BA, BB, BC, and BD) are tied to DGND.

I don’t believe there are any other pins left, but if you had a specific one you were curious about, let me know here.