Logic Analyzer project


I have experience with microcontrollers, embedded systems and such but I am still fairly new to the world of FPGAs. I would like to start working on a prototype for a custom logic analyzer and the XEM6310 looks like a good candidate, however I am unable to confirm that I can accomplish what I have in mind. Maybe someone can tell me if it is feasible so I can proceed to buy the product and start learning on it.

Basically, I want my logic analyzer to have at least 30 channels, which shouldn’t be a problem, but I want to be able to use a computer to interpret the data in real time. So what I think that implies is that I would somehow transfer the data to RAM which would serve as a buffer for the data to be sent to the computer hoping it keeps up and that the buffer doesn’t get filled.

Having worked with logic analyzers that operate in a similar fashion, I don’t think it would be a problem, however, every commercial option out there lacks in speed, inputs or customization options. Opal Kelly products look absolutely amazing and I know that logic analyzers have been built with them before, unfortunately their design are quite different from what I have in mind.

Thank you for your time.

On a side note, I was also wondering if the BRK6110 is still the right breakout board for the XEM6310 and if there is a way to use USB as a power source instead of an external power supply, given I don’t exceed the maximum current ratings for USB.

You can use the PC to manage the data in real time if you’re streaming it to the PC. Of course, you will lose some performance because you’ll be limited by the streaming rate back to the PC. The FPGA could capture 30 channels much faster than it could stream it back. You could use some hybrid approaches to do some processing in the FPGA and some on the PC – essentially reducing the information sent over USB.

Our EVB1005 and EVB100X-DEV would be a good start because they set things up in a streaming manner over the okPipes. FIFOs are used to smooth transfer to/from the DDR2 memory.

The BRK6110 is the proper board. You can power it via USB but as you suggest, you’ll want to be mindful of the power limits.

That’s exactly what I had in mind, customized triggers to reduce the data sent via USB, although I still wanted to make sure I can develop a real logic analyzer if need be. From what I gather, the board operates on a 100 MHz clock which I take it would be my maximum operating frequency. At that rate, I’d have to send my 30 channels, let’s say at least 4 bytes, on every clock cycle…400 MB/sec…still within the theoretical limits of the USB 3.0 specifications. I don’t know that a little C program could process that much data so fast.

Sorry, I’m just thinking ‘out loud’ here. I will purchase the board and give it a try. In the mean time, thanks for your help and if you have any other pointers to help me out, it would be really appreciated.

Thank you

The 100 MHz clock on the board is an input to the FPGA but you are certainly not limited to using just that clock. You can use the Spartan-6 clocking resources (DCM, PLL, etc.) to generate your own clock of almost any frequency. There are also very high-speed dedicated I/O clock buses available which might be usable for high-speed signal sampling and which operate faster than the general fabric clock routing. The USB3 host interface has a separate 100.8 MHz clock which (or a multiple of it) might be useful as a system clock if you want to minimize clock domain crossings.

If this were my project I would consider using the onboard SDRAM to store samples. I believe its maximum frequency with this FPGA is 312.5 MHz; since it’s DDR with a 16-bit bus that’s an effective maximum transfer rate of 10 Gbit/sec. The Spartan-6 built-in memory controller makes it easy to interface to the DDR2 memory in a flexible way, at the cost of some performance, but you could also write your own custom memory controller.

One more thing. I did a data streaming application using the XEM6310 where it acted as basically a large FIFO using the SDRAM, sending data to a Windows PC. I was getting about 300 MB/sec average data rates for large transfers, which I believe is also close to what the Opal Kelly benchmark program achieves. I don’t think you’re going to reach 400 MB/sec or higher with this setup.

Thanks a lot for all the help and tips, it sounds like that little board can do a lot of awesome things.

I was just about to buy it the other day when I started reading the disclaimer about the proprietary firmware and it suddenly made me a little hesitant. I have absolutely no doubts that this product is very highly capable but I originally thought it was just a custom made board of select parts put together, I never realized there was actually proprietary software running on it and that I could end up ‘bricking’ it.

Can anyone enlighten me on what this firmware does, where it sits and what this all really entails?

Thank you.

The firmware provides the FrontPanel capability. Please see the FrontPanel User’s Guide. If you stick to just programming the FPGA, you can’t “brick” the device.

While many FPGA modules are, as you suggest, just chips on a board, that is not our design. We provide value in the FrontPanel SDK that is not found on other boards. This is how we distinguish between our “integration modules” and other manufacturers’ “evaluation boards”.