Hello,
When I try to simulate in ModelSim my VHDL project that uses HostInterface functionality, I keep getting the following error message:
[INDENT][I]# vsim -L okFPsim -L unisim -t ps aes_TEST
Loading std.standard
Loading ieee.std_logic_1164(body)
Loading ieee.std_logic_arith(body)
Loading ieee.std_logic_unsigned(body)
Loading std.textio(body)
Loading ieee.std_logic_textio(body)
Loading ieee.numeric_std(body)
Loading ieee.math_real(body)
Loading work.aes_test(sim)
Loading lib_crypt.lib_crypt
Loading work.aes_crypto(behavioral)
Loading work.cfb(behavioral)
Loading work.aes(behavioral)
Loading work.control_aes(behavioral)
Loading work.key_expander(behavioral)
Loading work.s_box(behavioral)
Loading work.rcon(behavioral)
Loading work.encryption(behavioral)
Loading work.mux_2x1(behavioral)
Loading work.gen_s_box(behavioral)
Loading work.gen_mixcol(behavioral)
Loading work.mixcolumns(behavioral)
Loading work.x2_ffmul(behavioral)
Loading work.key_register(behavioral)
Loading work.vector_register(behavioral)
Loading work.sh_input(comport)
Loading work.ram_out(ram_out_a)
Loading xilinxcorelib.blk_mem_gen_v2_7(behavioral)
Loading xilinxcorelib.blk_mem_gen_v2_7_output_stage(behavioral)
** Error: (vsim-13) Recompile okfpsim.okhostinterface because ieee.std_logic_1164 has changed.
** Error: (vsim-13) Recompile okfpsim.okhostinterface(arch) because ieee.std_logic_1164 has changed.
Load interrupted
Error loading design[/I][/INDENT]
I went through all the steps described in the part 4 of the tutorial, and I can’t understand why this is happening. Any help would be greatly appreciated.
Regards,
Vitor