IsFrontPanelEnabled() ----> "False" (w/ Python & "First" Example)


I can connect my ZEM5310, load it with the “First” image, and successfully get the “First.XFP” to control the onboard LEDs via the FrontPanel GUI.

When I try to do the same w/ Python, the response from it is that my “OkHost” interface isn’t up and working…



This explains why my SetWireInValue, UpdateWireIns, etc commands are not working…

But why is dev.IsFrontPanelEnabled() coming back as “False”? Why does the “First.XFP” profile work?




Sanity check: try using our First bitfile to determine if the problem is with your HDL / bitfile creation.


Can you provide that, or provide a location for that file?

In the Opal Kelly -> FrontPanelUSB -> bitfiles -> ZEM5310-A4 -> flashloader.bit (Is the only .bit file available)

In Opal Kelly -> FrontPanelUSB -> Samples -> First -> ZEM5210-VHDL -> .VHD & .QSF (Are the only files)

Please point me to where this “First.bit” resides.




I just grabbed the First.RBF from the ZEM5310 Bitfiles on your downloads section…

I am still able to get the serial number, and open the device via python… but still get a “False” when I run the dev.IsFrontPanelEnabled()


Okay, I think I have found a issue.

I thought a .rbf was saved in memory… so upon bootup it gets re-loaded by default.

Well I was downloading the .rbf to the target device, cycling power (thinking I needed to do that) and then running my python commands.

I found that if I load a .rbf, and don’t cycle power, I can close FrontPanelGUI, start my python session, and see that when I run the “dev.IsFrontPanelEnabled()” that I finally get TRUE.

Just wanted to update on my progress…


FPGAs are generally volatile (SRAM-based) devices. You configure them and that configuration works until power cycle or reconfiguration.

We encourage newcomers to work through the Getting Started Guide first:

But generally our documentation is not aimed at those unfamiliar with FPGAs. You may want to start with some tutorials or introductory materials available elsewhere online or through Xilinx.