ISE 11.2 Place and Route Error with "Counters"

Spartan-3 USB 2.0 Modules
1

Hi,
Latest ISE 11.2 WebPack Place and Route gives the following error (converted by me to a warning by

NET “clk1” CLOCK_DEDICATED_ROUTE = FALSE;
)

[INDENT]WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component is placed at site . The IO component is
placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is
normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to
continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override
is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design.[/INDENT]

Any ideas why I’m getting this and how this could be corrected?

Thanks!

2

The CLOCK_DEDICATED_ROUTE constraint is added to prevent an error condition in the P&R tools. You can remove this constraint to read more about the error.

3

— Begin quote from Opal Kelly Support;2537

The CLOCK_DEDICATED_ROUTE constraint is added to prevent an error condition in the P&R tools. You can remove this constraint to read more about the error.

— End quote

Yes, I’ve added the CLOCK_DEDICATED_ROUTE=FALSE to be able to complete the project by converting this error to a warning. I think the text of the error is repeated in the first part of the warning above.

Any idea what needs to be corrected? Tying the clock line to A8 is locked in hw and seems to be correct. Where comes from?

4

This is a newer warning with the newer tools and I’m not sure where it comes from. If you don’t sync anything else to the external clk1 (you really can’t on our boards), then this shouldn’t be an issue at all.

5

— Begin quote from Opal Kelly Support;2539

This is a newer warning with the newer tools and I’m not sure where it comes from. If you don’t sync anything else to the external clk1 (you really can’t on our boards), then this shouldn’t be an issue at all.

— End quote

My concern is how to use clk1 in 3005 connected to A8 efficiently as a global clock.

From the datasheet it appears that in 1200E-FT256 A8 corresponds to GCLK8.

If is placed at site it corresponds to I0 input of that can source only GCLK5 or GCLK9
(
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
“Using Global Clock Resources”)

I’m not sure - but it would seem that if can be placed at site instead, - things could work. (See Table 2-7 in the above UG)

I don’t understand who influenced an inefficient placement causing the error/warning - one would think the tools should figure this out. Is there any constraint implicit in ithe “Ok” cores that may cause this? Any other ideas?