Using Pipetest.v / Pipetest.exe / XEM3010 / okBTPipeIn
The manual implies that ti_clk is 48 MHz but the data width to the BRAMs is always implemented as 16-bit wide (for a pipe), not 8. Given that USB 2.0 is 480 MHz (eqv 48 MByte/S after start/stop bits), something has to give.
Is the same BRAM address read/written twice at 48 MHz or once at 24MHz? … or is the Cypress part buffering somewhere ???
- sorry in advance if I’m missing something obvious.