Is there a way to reduce the OkClk frequency?

As the title says, I want to reduce the OkClk frequency coming from the front panel USB. I use XEM7310-200 with USB3 which has a frequency of 100.8 MHz.

With my HDL to receive data from front panel and sends it out to an external hardware, I see setup timing violations using 100.8MHz frequency, so I wanted to reduce the frequency.

I thought about having 2 clock domains but it also produced violations.

IF there are alternatives to my thoughts please let me know.

You could either use the okClk, or the onboard clock oscillator, to feed the clock management tiles (CMT) of the 7-series device. See the following documentation for more information:
And information about the onboard clock oscillator for the XEM7310-200 is located here:

The timing engine will produce many timing violations for an unconstrained design. You need to relieve the engine of certain CDC paths after you’ve established them. Violations that are a result of CDC become pretty apparent from the tools trying to achieve an unreasonable timing window. Reducing the clock frequency will not resolve the timing issues related to CDC. You’ll need to inform the timing engine to ignore these paths.

100.8 MHz, ~10ns, is a pretty reasonable window to achieve timing. If you are in fact violating timing on a path between two clocked elements utilizing this clock, i.e. Intra-Clock Paths, then either reducing the frequency, or pipelining the critical path somewhere near the middle of the path will resolve the timing violation.

You can read about clock groups here:

You can read about CDC constraints here: Documentation Portal


Is it safe to use both sources (osc and usb)? I want to do so because i need a 200MHz clock and also a smaller freq clk for my chip that i am testing with the OK board. Since I need to send data from the OK front panel, I have to use the USB clk along with the osc.

Does that make sense?