Is it possible to simulate the Host Interface from VHDL?

I have opal kelly ngc files converted to gatelevel VHDL for FPGA simulation using the following trick:

export PATH=/cygdrive/s/eti/EDA/xilinx/suite/14.7/ISE_DE/ISE/bin/nt:$PATH
netgen -ofmt vhdl  okHostInterfaceCore.ngc
netgen -ofmt vhdl  okPipeOut.ngc
netgen -ofmt vhdl  okPipeIn.ngc


it simulates without error…

Now i’m wondering is it possible to drive the inputs opal kelly host interface from testbench to emulate Front panel API calls? so that i can test the design entirely in simulation without downloading the fpga boards and conecting PC host with front panel… for instance, let’s say i have the following instantiation design instance…

ok_host : entity work.okHostInterface port map(    
    – Host Interface to FPGA Board
    ti_clk    => hi_clk,    – o     
    hi_in     => HI_IN,     – i[7:0]
    hi_out    => hi_out,    – o[1:0]
    hi_inout  => HI_INOUT,  – b[15:0]
    – OK Bus
    ok1       => ok1,       – o[30:0]
    ok2       => ok2        – i[16:0]

from the testbench i want to drive and monitor the post hi_in, hi_out, hi_inout from testbench of okHostInterface… I have some legacy code that attempts to do this… i have no idea where it came from…or if this was something that opal kelly once supported?! I’ll give you a little sample of what they are trying to do:

from testbench:

write(output, “-> FrontPanelReset” & LF);
  FrontPanelReset (usb_clk => HI_IN(0), command => HI_IN(7 downto 4), busy => HI_OUT(0));

from package:

procedure FrontPanelReset (
      signal usb_clk     : in    std_logic;
      signal command     : out   std_logic_vector(7 downto 4);
      signal busy        : in    std_logic);

procedure WriteToPipeIn (
      signal   usb_clk     : in    std_logic;
      signal   command     : out   std_logic_vector(7 downto 4);
      signal   write       : out   std_logic;
      variable length      : in    integer;
      variable pipein      : in    pipein_array;
      signal   hi_inout    : inout std_logic_vector(15 downto 0);
      signal   busy        : in    std_logic);


Does opal Kelly have this capability? is there some testbench package laying around somewhere that emulates Frontpanel API from simulation testbench, (no need for the gui…) just want procedure like interface for testing…


(NOTE: these posts were not posted by the jerks who secretly watch my computer screen at work and copy and pretend my work is there’s… so sick of that scam i could puke… obviously the person who did the work is the poor contractor working along that do the work and then gets kicked out and some other contractor jerk gang puts their name on his work and milks the contract with more fake projects…)

I was about to guess that host-interface maps internally to the following:

– HI_IN(0)              <= HI_CLK;              --Input Host interface clock signal.
    – HI_IN(1)              <= HI_CS;               --Input Active-low chip select.
    – HI_IN(2)              <= HI_RDWR;             --Input Read (high) / Write (low) signal.
    – HI_IN(7:3)            <= HI_ADDR(3 downto 0); --Input Host interface address lines.
    – HI_IRQ                <= HI_OUT(0);           --Output Interrupt request to USB micro-controller.
    – HI_BUSY               <= HI_OUT(1);           --Output Host interface busy signal.
    – HI_DATA_W             <= HI_INOUT(15 downto 0);
    – HI_INOUT(15 downto 0) <= HI_DATA_R when HI_RDWR = ‘1’ else X"00";

Or something like this…

I’m guessing a monitoir can be made for the Opal kellyhost-interface:

signal OK_HI_IRQ         : std_logic;     
  signal OK_HI_BUSY        : std_logic;     
  signal OK_HI_CLK         : std_logic;    
  signal OK_HI_CS_N        : std_logic;    
  signal OK_HI_RDWR        : std_logic;
  signal OK_HI_ADDR        : std_logic_vector(3 downto 0);
  signal OK_HI_DATA_R      : std_logic_vector(15 downto 0);
  signal OK_HI_DATA_W      : std_logic_vector(15 downto 0);

ipsrfapd_f   <= ‘H’;
ipsrfarst_f  <= ‘H’;

– The O.K. Host Interface Monitor

OK_HI_IRQ     <= HI_OUT(0);          
OK_HI_BUSY    <= HI_OUT(1);          
OK_HI_DATA_W  <= HI_INOUT(15 downto 0)  when OK_HI_RDWR = ‘0’ else X"0000";
OK_HI_CLK     <= HI_IN(0);            
OK_HI_CS_N    <= HI_IN(1);         
OK_HI_RDWR    <= HI_IN(2);         
–OK_??       <= HI_IN(3); --??
OK_HI_ADDR    <= HI_IN(7 downto 4);
OK_HI_DATA_R  <= HI_INOUT(15 downto 0)  when OK_HI_RDWR = ‘1’ else X"0000";

what i need is a rep from the company or somebody experienced with their product to help make sure this is the correct signal mapping…

Hi there,

We have a working and established set of simulation files for USB2.0 VHDL. The First sample, located by default in your C:/Program Files/Opal Kelly/FrontPanelUSB/Samples/First folder, contains simulation examples and READMEs. To simulate it in VHDL, copy the contents of the First folder to a work folder and follow the instructions in the README and First_tf.vhd files located in First/Simulation-USB-VHDL.

Please note that your Opal Kelly installation folder may be in a different location if you changed the location while installing FrontPanel on your computer.


Please also refer to the “FrontPanel Host Simulation” section in the FrontPanel User’s Manual.