We were able to recreate your issue related to SYZYGY Port C on the XEM8320 board. After a thorough investigation, it seems the problem lies with the timing of the LVDS DDR Source synchronous interface. We’ve addressed this issue in our latest commit:
Fix ADC-14 timing: Implemented MMCM phase shift in ADC sample design
To resolve your issue, checkout this commit, re-target the interface for Port C in the XDC (instead of Port A), and test the new bitfile in-hardware. This should solve your problem.
Please report back with your results. Looking forward to your update.