I am using xem8320 board and trying to interface ADC-LTC226x(14 bit) in the standard ports A,B,C and D. Though data transmission through A and B port is possible but Port C and D are not processing my desired data. I have changed the constraint file(pin numbers) for C and D but Vivado shows error in IO banks. What should I do in this context? Is it possible to change the IO banks and make it similar to Port A and B?
Through Port C, data is coming but lossy, when it is supposed to display a fine sine wave. What modifications can be done for PORT-C so that it behaves like PORT A and B?
Hello and welcome to the forums!
Could you please post all the error messages you are seeing so we can get a better idea of the issue here?
Additionally, please confirm your XDC file is correct for the desired Syzygy port using our Pins tool.
PORT D shows: [DRC BIVB-1] Bank IO standard Support: Bank 84 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
adc_dco_p.
PORT C shows the attached waveform instead the fine sinusoidal signal (input to ADC).
Note: The XDC file is changed according to the PORT numbers as given in your site : Pins: XEM8320
The XDC file for Port C is given here:
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
############################################################################
FrontPanel Host Interface
############################################################################
set_property PACKAGE_PIN U20 [get_ports {okHU[0]}]
set_property PACKAGE_PIN U26 [get_ports {okHU[1]}]
set_property PACKAGE_PIN T22 [get_ports {okHU[2]}]
set_property SLEW FAST [get_ports {okHU[*]}]
set_property IOSTANDARD LVCMOS18 [get_ports {okHU[*]}]
set_property PACKAGE_PIN V23 [get_ports {okUH[0]}]
set_property PACKAGE_PIN T23 [get_ports {okUH[1]}]
set_property PACKAGE_PIN U22 [get_ports {okUH[2]}]
set_property PACKAGE_PIN U25 [get_ports {okUH[3]}]
set_property PACKAGE_PIN U21 [get_ports {okUH[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {okUH[*]}]
set_property PACKAGE_PIN P26 [get_ports {okUHU[0]}]
set_property PACKAGE_PIN P25 [get_ports {okUHU[1]}]
set_property PACKAGE_PIN R26 [get_ports {okUHU[2]}]
set_property PACKAGE_PIN R25 [get_ports {okUHU[3]}]
set_property PACKAGE_PIN R23 [get_ports {okUHU[4]}]
set_property PACKAGE_PIN R22 [get_ports {okUHU[5]}]
set_property PACKAGE_PIN P21 [get_ports {okUHU[6]}]
set_property PACKAGE_PIN P20 [get_ports {okUHU[7]}]
set_property PACKAGE_PIN R21 [get_ports {okUHU[8]}]
set_property PACKAGE_PIN R20 [get_ports {okUHU[9]}]
set_property PACKAGE_PIN P23 [get_ports {okUHU[10]}]
set_property PACKAGE_PIN N23 [get_ports {okUHU[11]}]
set_property PACKAGE_PIN T25 [get_ports {okUHU[12]}]
set_property PACKAGE_PIN N24 [get_ports {okUHU[13]}]
set_property PACKAGE_PIN N22 [get_ports {okUHU[14]}]
set_property PACKAGE_PIN V26 [get_ports {okUHU[15]}]
set_property PACKAGE_PIN N19 [get_ports {okUHU[16]}]
set_property PACKAGE_PIN V21 [get_ports {okUHU[17]}]
set_property PACKAGE_PIN N21 [get_ports {okUHU[18]}]
set_property PACKAGE_PIN W20 [get_ports {okUHU[19]}]
set_property PACKAGE_PIN W26 [get_ports {okUHU[20]}]
set_property PACKAGE_PIN W19 [get_ports {okUHU[21]}]
set_property PACKAGE_PIN Y25 [get_ports {okUHU[22]}]
set_property PACKAGE_PIN Y26 [get_ports {okUHU[23]}]
set_property PACKAGE_PIN Y22 [get_ports {okUHU[24]}]
set_property PACKAGE_PIN V22 [get_ports {okUHU[25]}]
set_property PACKAGE_PIN W21 [get_ports {okUHU[26]}]
set_property PACKAGE_PIN AA23 [get_ports {okUHU[27]}]
set_property PACKAGE_PIN Y23 [get_ports {okUHU[28]}]
set_property PACKAGE_PIN AA24 [get_ports {okUHU[29]}]
set_property PACKAGE_PIN W25 [get_ports {okUHU[30]}]
set_property PACKAGE_PIN AA25 [get_ports {okUHU[31]}]
set_property SLEW FAST [get_ports {okUHU[*]}]
set_property IOSTANDARD LVCMOS18 [get_ports {okUHU[*]}]
set_property PACKAGE_PIN T19 [get_ports okAA]
set_property IOSTANDARD LVCMOS18 [get_ports okAA]
create_clock -period 9.920 -name okUH0 [get_ports {okUH[0]}]
set_input_delay -clock [get_clocks okUH0] -max -add_delay 8.000 [get_ports {okUH[*]}]
set_input_delay -clock [get_clocks okUH0] -min -add_delay 9.920 [get_ports {okUH[*]}]
#set_multicycle_path -setup -from [get_ports {okUH[*]}] 2
set_input_delay -clock [get_clocks okUH0] -max -add_delay 7.000 [get_ports {okUHU[*]}]
set_input_delay -clock [get_clocks okUH0] -min -add_delay 2.000 [get_ports {okUHU[*]}]
#set_multicycle_path -setup -from [get_ports {okUHU[*]}] 2
set_output_delay -clock [get_clocks okUH0] -max -add_delay 2.000 [get_ports {okHU[*]}]
set_output_delay -clock [get_clocks okUH0] -min -add_delay -0.500 [get_ports {okHU[*]}]
set_output_delay -clock [get_clocks okUH0] -max -add_delay 2.000 [get_ports {okUHU[*]}]
set_output_delay -clock [get_clocks okUH0] -min -add_delay -0.500 [get_ports {okUHU[*]}]
############################################################################
System Clock
############################################################################
set_property IOSTANDARD LVDS [get_ports sys_clkp]
set_property PACKAGE_PIN T24 [get_ports sys_clkp]
set_property PACKAGE_PIN U24 [get_ports sys_clkn]
set_property IOSTANDARD LVDS [get_ports sys_clkn]
create_clock -period 10.000 -name sys_clk [get_ports sys_clkp]
set_clock_groups -asynchronous -group [get_clocks sys_clk] -group [get_clocks {mmcm0_clk0 okUH0}]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets idelay_adc_enc_clk/inst/clk_in1_clk_wiz_0]
LEDS
set_property PACKAGE_PIN G19 [get_ports {led[0]}]
set_property PACKAGE_PIN B16 [get_ports {led[1]}]
set_property PACKAGE_PIN F22 [get_ports {led[2]}]
set_property PACKAGE_PIN E22 [get_ports {led[3]}]
set_property PACKAGE_PIN M24 [get_ports {led[4]}]
set_property PACKAGE_PIN G22 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led[*]}]
##########################################################
ADC Section
##########################################################
PORTC-5
set_property PACKAGE_PIN F20 [get_ports {adc_out_1p[0]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_1p[0]}]
PORTC-6
set_property PACKAGE_PIN C18 [get_ports adc_fr_p]
set_property IOSTANDARD LVDS [get_ports adc_fr_p]
PORTC-7
set_property PACKAGE_PIN E20 [get_ports {adc_out_1n[0]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_1n[0]}]
PORTC-8
set_property PACKAGE_PIN C19 [get_ports adc_fr_n]
set_property IOSTANDARD LVDS [get_ports adc_fr_n]
PORTC-9
set_property PACKAGE_PIN H18 [get_ports {adc_out_1p[1]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_1p[1]}]
PORTC-10
set_property PACKAGE_PIN H17 [get_ports {adc_out_2p[0]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_2p[0]}]
PORTC-11
set_property PACKAGE_PIN H19 [get_ports {adc_out_1n[1]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_1n[1]}]
PORTC-12
set_property PACKAGE_PIN G17 [get_ports {adc_out_2n[0]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_2n[0]}]
PORTC-13
set_property PACKAGE_PIN F18 [get_ports adc_sdo]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sdo]
PORTC-14
set_property PACKAGE_PIN A17 [get_ports {adc_out_2p[1]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_2p[1]}]
PORTC-15
set_property PACKAGE_PIN F19 [get_ports adc_cs_n]
set_property IOSTANDARD LVCMOS18 [get_ports adc_cs_n]
PORTC-16
set_property PACKAGE_PIN A18 [get_ports {adc_out_2n[1]}]
set_property IOSTANDARD LVDS [get_ports {adc_out_2n[1]}]
PORTC-17
set_property PACKAGE_PIN E16 [get_ports adc_sck]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sck]
PORTC-19
set_property PACKAGE_PIN E17 [get_ports adc_sdi]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sdi]
PORTC-33
set_property PACKAGE_PIN E18 [get_ports adc_dco_p]
set_property IOSTANDARD LVDS [get_ports adc_dco_p]
PORTC-34
set_property PACKAGE_PIN C17 [get_ports adc_encode_p]
set_property IOSTANDARD LVDS [get_ports adc_encode_p]
PORTC-35
set_property PACKAGE_PIN D18 [get_ports adc_dco_n]
set_property IOSTANDARD LVDS [get_ports adc_dco_n]
PORTC-36
set_property PACKAGE_PIN B17 [get_ports adc_encode_n]
set_property IOSTANDARD LVDS [get_ports adc_encode_n]
ADC timing constraints
create_clock -period 6.250 -name adc_dco_p -waveform {0.000 3.125} [get_ports adc_dco_p]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -min -add_delay 1.090 [get_ports {adc_out_1n[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -max -add_delay 2.035 [get_ports {adc_out_1n[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -min -add_delay 1.090 [get_ports {adc_out_1n[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -max -add_delay 2.035 [get_ports {adc_out_1n[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -min -add_delay 1.090 [get_ports {adc_out_1p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -max -add_delay 2.035 [get_ports {adc_out_1p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -min -add_delay 1.090 [get_ports {adc_out_1p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -max -add_delay 2.035 [get_ports {adc_out_1p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -min -add_delay 1.090 [get_ports adc_fr_n]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -max -add_delay 2.035 [get_ports adc_fr_n]
set_input_delay -clock [get_clocks adc_dco_p] -min -add_delay 1.090 [get_ports adc_fr_n]
set_input_delay -clock [get_clocks adc_dco_p] -max -add_delay 2.035 [get_ports adc_fr_n]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -min -add_delay 1.090 [get_ports adc_fr_p]
set_input_delay -clock [get_clocks adc_dco_p] -clock_fall -max -add_delay 2.035 [get_ports adc_fr_p]
set_input_delay -clock [get_clocks adc_dco_p] -min -add_delay 1.090 [get_ports adc_fr_p]
set_input_delay -clock [get_clocks adc_dco_p] -max -add_delay 2.035 [get_ports adc_fr_p]
set_clock_groups -name decode_reset_group -asynchronous -group [get_clocks -of_objects [get_pins okHI/mmcm0/CLKOUT0]] -group [get_clocks adc_dco_p]
set_clock_groups -name adc_data_clk_reset -asynchronous -group [get_clocks -of_objects [get_pins okHI/mmcm0/CLKOUT0]] -group [get_clocks -of_objects [get_pins adc_impl/adc_dco_impl/adc_dco_bufr/O]]
set_clock_groups -name mmcm_clk_reset -asynchronous -group [get_clocks -of_objects [get_pins adc_impl/adc_dco_impl/adc_dco_bufr/O]] -group [get_clocks -of_objects [get_pins idelay_adc_enc_clk/inst/mmcme4_adv_inst/CLKOUT0]]
For port D, the behavior you’re encountering is expected due to limitations on the HD banks of the FPGA. Port D does not support differential standards. You can find more information on this in our XEM8320 - SYZYGY Ports documentation. Please refer to the SYZYGY Compatibility Table, where you will see a note [1] that states, “The I/O on this port do not support differential standards because of limitations on HD banks.”
Regarding Port C, I have verified the FPGA pin locations in the XDC file you’ve shared, and didn’t find any inconsistencies. I built this project to bitfile, during which I reviewed the warnings log and did not spot any issues of concern. The bitfile seems to have been built without any problems.
We will look into this further and report back once we have more information.
Thanks for your support. PortC generates the bit file like other ports but we are not getting the desired output as we got for PORT-A and B (for same input). I am attaching the screenshots of the input given from signal generator and also attaching the waveform(output) we’ve got for PORT-B(desired output) and PORT-C, so that you can compare them.
- 3rd image/waveform is for PORT-B at 1MHz.
- 4th image/waveform is for PORT-B at 3MHz.
- 7th image/waveform is for PORT-C at 1MHz.
- 8th image/waveform is for PORT-C at 3MHz.
- 9th image/waveform is for PORT-C at 100 KHz.
Dear,
Still we have not found any solution on the above mentioned problem regarding SYZYGY Port C of XEM8320 board. We are eagerly looking for your kind update.
Thanks…
We were able to recreate your issue related to SYZYGY Port C on the XEM8320 board. After a thorough investigation, it seems the problem lies with the timing of the LVDS DDR Source synchronous interface. We’ve addressed this issue in our latest commit:
Fix ADC-14 timing: Implemented MMCM phase shift in ADC sample design
To resolve your issue, checkout this commit, re-target the interface for Port C in the XDC (instead of Port A), and test the new bitfile in-hardware. This should solve your problem.
Please report back with your results. Looking forward to your update.
Thanks for your support. And it works. Could you also suggest me something so that I can operate all the 3 ports(PORT-A,B,C) together using 3 ADCs? I mean I want to perform 6-channel transmission.