I/O Pin - Logical 1 and Logical 0

Hi,

I am thinking about attaching photodiodes to the FPGA’s I/O pins, and I was just wondering what is the threshold for logical 0s and 1s for the FPGA. For example, if FPGA reads 2.5V at its I/O pin as input, is that going to be interpreted as a ‘1’ or ‘0’? My assumption is the 70/30 rule, where if the VDD is 3.3V, then 3.30.7=2.31V and above are logical ‘1s’ and 3.30.3=0.99V and below are logical ‘0s’ and the things in between are U - Undefined.

Can you please let me know if this is right? If not, what is the correct scheme?

Also, can any1 validate my assumption that when FPGA writes a logical ‘1’ at it’s I/O pin as output, it writes 3.3V and when it writes a logical ‘0’ it does 0V or GND.

Thanks,
Larry Chen

Larry–

Please see the Xilinx Spartan-3 documentation for a thorough answer on this topic. Note that the VCCO are tied to 3.3v on the XEM3001.

Opal Kelly Support

Ok thanks for letting me know.

Hi, this is a related question as it pertains to the Pin Out definitions of the board.

I read the XEM3001v2 User?s Manual (
http://www.opalkelly.com/library/XEM3001v2-UM.pdf
) and it says that connections of JP2 are connected to bank 6 and 7 pins of the FPGA, while only some are directly connected to static values such as VDD or GND. So does this mean that for pins that are connected to VDD or GND, they connect the respective FPGA pins to VDD or GND? ie. JP2 pin 1 and 2 connect FPGA Bank 6 and 7 Pin 1 and 2 to GND?

Because if this is the case, I have a question about that. On page 13 of the XEM3001v2 User?s Manual, it shows that JP2 pin 8 is an IO pin, and pin 10 is connected to 3.3V VDD, respectively. If this meant that FPGA bank 6 and bank 7’s pins are connected to the corresponding values, it seems to contradict with that Spartan 3 documentation says (


). On page 140 of the Spartan 3 documentation, it shows that FPGA Bank 6 and 7’s pin 8 and pin 10 are GND and general purpose IO, respectively. So basically in this case the XEM3001v2 User?s Manual seems to suggest that pin 8, which is a GND pin, as an IO pin, and pin 10, which is a general purpose IO, as a 3.3V VDD pin.

If some1 can help explain this, I would really apprecaite it.

Thanks,
Larry Chen

I’m not sure what is confusing you, so let me explain the Quick Reference in the XEM3001v2:

For the column marked “JP2”, the contents of each row refers to the pin on that connector.

For the column marked “Connection”, the contents refer to how that pin is connected. If DGND, it means that the pin is connected to DGND. If +3.3VDD, the pin is connected to +3.3VDD. If something like “I/O 11”, it means it is connected to FPGA pin 11.

So,
JP2 pin 1 and 2 connect to DGND.
JP2 pin 8 connects to FPGA pin 10.
JP2 pin 10 connects to +3.3VDD.

JP2 pins happen to be connected to FPGA banks 6/7, but that is not to imply that the same pin numbers of the two devices are directly connected.

Thanks. I will look into this.