How to use okLibrary

Hi, we are wondering how to simulate the okHostInterface.

Do you provide a simulation model, or documentation to describe how the interface works? Such as handshaking, clock implementation, etc.?

Any simulation model would be good so we can simulate, but we need at least documentation. We just have the ngc binaries for now, but we cannot simulate these.


Please see the following sources:

  1. FrontPanel User’s Manual – There is a brief introduction to the Host Interface simulation here that describes the setup required.

  2. Online tutorial (see the “Support” page on our website) – Part IV discusses simulation using our models for ModelSim.

  3. The samples included with your installation. Notably, the First and DESTester samples have simulations in the XEM3001v2 source directories. You should be able to use these samples as a basis for your own test fixture.

Ok… please bare with me here. I’m new to forums and don’t know the educate…

With that said, I am trying to find more information on the Host Interface that was supplied with FP v1.3.1. I did read the previous post and the manual that came with that CD pkge. What I need to know more of is why in my simulation of “First” sample I do not see hi_busy do anything and also how exactly does hi_dir work with the hi_rdwr… once I understand these signals and their operation I can continue on my other project. In that project these two issues have brought it to a “stand-still”.

If anyone has some info that could help, I would be greatly appreciative…




The host interface simulations are designed to simulate two interfaces:

  1. The PC-side calls to the API (as best the HDL can allow)
  2. The endpoint interface where your logic connects (like to the okPipeIn and such)

Everything else in between is not necessarily an accurate portrayal of what is going on. Specifically, HI_BUSY, HI_DIR, etc. They’re irrelevant.

Right… Ok I see that… but still nothing coming out to the ep for my logic to use… Funny you should use that example “okPipeIn” because that is what I am working with… and I don’t see the data on the ti_data signal… pretty sure that my components are setup correctly. Who knows…

In your first post, you said you were trying to simulate the First sample. In this last post, you mention the okPipe. First does not have an okPipe instance.

Sorry… Let me clarify…

I started a project by writing the GUI (in C) first using the DLL and loading the First.bit file to make sure I could do that. Worked great and was able to control the LEDs as I wished. Next I started with the lower modules of the HDL design which, will use okPipeIn and okTriggerIn… so, as I always do I simulate each module up to the top level. Once I started to simulate the top level with the Generic Test Bench (which was setup for the Pipe tests) I would get nothing into my end points. Figured I had something wrong… So, I took a set back and tried to see how it operated woth the First sample. I have been able to synth itand create a bit file that I loaded and tested… however, I have not been able to simulate it successfully to see how I need to sim my project. When I sim the first sample nothing makes it to the end point… so, in the end it loks like I need to take my project back to the orig serial port project becuase I need to send it to our other division wednesday.

Thanks though,