I am somewhat confused about the power supply requirements for I/O banks for LVDS.
Ok, suppose that I want to use Bank 6 to receive LVDS data signals, so I supply 2.5V to bank 6 VCCO (remove the ferrite bead on XEM3010 etc etc…).
I also need to receive an LVDS clock, and need to use a pair of complementary GCLK’s, which are in Bank 0, not in Bank 6.
Problem: how do I supply DC power to these GCLK’s without messing up the rest of Bank 0?? In other words, if I supply 2.5V VCCO to bank 0, the GCLK’s will be powered up for LVDS, but so will be the rest of bank 0, which I don’t want.
I haven’t been able to find the answer in Xilinx documentation (yet).