I am somewhat confused about the power supply requirements for I/O banks for LVDS.
Ok, suppose that I want to use Bank 6 to receive LVDS data signals, so I supply 2.5V to bank 6 VCCO (remove the ferrite bead on XEM3010 etc etc…).
I also need to receive an LVDS clock, and need to use a pair of complementary GCLK’s, which are in Bank 0, not in Bank 6.
Problem: how do I supply DC power to these GCLK’s without messing up the rest of Bank 0?? In other words, if I supply 2.5V VCCO to bank 0, the GCLK’s will be powered up for LVDS, but so will be the rest of bank 0, which I don’t want.
I haven’t been able to find the answer in Xilinx documentation (yet).
Unfortunately, you’re stuck with bank-by-bank selections. If you need to use multiple supplies for a bank, you will need to pick a supply and use level-translators for the signals on the bank that don’t fit.
How does everyone use LVDS on XEM3010 then?
The only differential clock pairs available on XEM3010 are GCLK6/7 which belong to bank 0, and GCLK4/5 which belong to bank 1.
JP2 and JP3 do not have provisions to control bank 0 and bank 1 VCCO.
How can I receive LVDS clock? (without using general I/O as clock).
Two notes. Using LVDS does not necessarily require that LVDS be used for clocking.
For the specific case where you need to receive an LVDS clock, however, you may want to refer to this topic:
http://forums.opalkelly.com/showthread.php?t=47
(See the reference to a Xilinx answer record near the end of the topic.)
Inputs are not VCCO dependent.
That makes a lot of sense!
Well, the details depend on specific situations, as the answer record addresses.
Generally, however, inputs are VCCO-dependent as the VCCO is used to set input thresholds in the I/O architecture.