I am using a XEM7310 board to test a custom chip. I am using OK wireIns, TriggerOuts, pipe ins and outs too in my design. I run RTL simulations and it works fine. Unfortunately when I run it on the actual board, I see some data missing in pipeOut (probably a sync issue in my verilog). So, I wanted to run post-synthesis simulation to fix that bug.
Is there like a tutorial for this? I feel I am missing something.
Here is what I tried, I added some files from the OK simulation dir to my vivado project, these files are:
okHostCalls.v and parameters.v. That’s besides the testbench ofc.
I didn’t add any other file from the oksim dir since I assumed vivado already has the encrypted version of the OK IPs (wires, pipes, etc).
Am I wrong here? and how to do it the right way?