How to map End points

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1

hi,
According to DES example given in sample folder,in sample code

for (i=0; ih04), .ep_dataout(des_key[15:0]));

thank you

regards,
duleep

2

Generally, yes, you would need to instantiate multiple WireIn endpoints. Here’s how we do it in the DES sample (VHDL edition) which should have been included with your samples:

wiregen: for i in 0 to 3 generate begin
    ep08 : okWireIn port map (
            ti_clk => ti_clk, ti_control => ti_control, ti_data => ti_data,
            ep_addr => std_logic_vector(TO_UNSIGNED(i+8, 8)),
            ep_dataout => des_key(i*16+15 downto i*16));
end generate;

Note that this uses the gnerate statement in VHDL, but is certainly not required.