How to generate *.bit file by myself?

Specifically for the example of RAMTester.
In ISE9.1, I generated the “fifo16w16r_2048.v” by “fifo16w16r_2048.xco”, and added it to the project.
I tried the top-level source type both as “ngc/ngo” and “HDL”, added the 3 verilog files in “XEM3010-verilog” as well as the “xem3010.ucf”, and the okLibrary.v plus all the *.ngc files from “FrontPanelHDL\XilinxISE82”.
The project failed when generating the programming file.
The error is “ramtest.v line 37 Illegal redeclaration of ‘fifo16w16r_2048’, module fifo16w16r_2048 compiled, module ramtest compiled, Analysis of ram_test.prj failed”.

What steps shall I take to generate the ramtest.bit file by myself?
In readme.txt, there are some instructions for example of “counter”. But for “Ramtester” there should be another one.

Thanks for your answering!


The .xco file indicates that the fifo16w16r is a Xilinx Core. The .xco file is used by the Core Generator to recreate the core. Please see the Xilinx documentation on Core Generator to see how to do this.

We have pre-compiled this core for you, however, and include the fifo16w16r_2048.ngc file in the samples directory. You do not need to rebuild this unless you want to fiddle with Core gen.

As with the other cores, you shouldn’t need to add the .ngc file to your project – just keep it in the project directory.

I did as you instructed. Now the new problem is at “Mapping”.
They are similar beginning with “MapLib:661”. One of them is
“MapLib:661 - LUT4 symbol “okHI/hicore/_mux00021” (output signal=okHI/hicore/_mux0002) has input signal “okHI/hicore/_xor0001” which will be trimmed. See the trim report for details about why the input signal will become undriven.”
Please let me know what happened. Thank you very much!!!

Are these errors or warnings?

Errors. So I can not continue any more.

Sorry, I’m not sure. The samples all build just fine under ISE 8.x, 9.x, and 10.x here. If you follow the instructions in the README, you should be fine. The only thing that changes is that you’ll have more *.v sources and you need to copy the fifo .ngc file to your project directory.

So, tell us specifically how you have things setup – which files are part of your project? Which .ngc files are in the project directory? Also, please attach the entire output from the ISE steps.

I already fixed the problem. Thank you for your help.:slight_smile:

@guming1-- For posterity, can you please share what the problem was and how you fixed it?

  1. Create a new project in ISE9.2. Be careful to choose the correct configuration for your FPGA. And for the “top level source type” in the first step, just choose “HDL”. (That’s why I made mistakes since I chose “NGC/NGO” to let in the *.ngc files).
  2. Copy files to the new project directory from the directory of “RAMTester\XEM3010-Verilog”, including *.v files, *.ngc files and the xem3010.ucf .
  3. Copy files to the new project directory from the directory of “FrontPanelHDL\XilinxISE82”, including *.v files and *.ngc files.
  4. Add all the *.v files and the xem3010.ucf currently in your project directory to the project.
  5. Generate the programming file and download it to your FPGA.