Specifically for the example of RAMTester.
In ISE9.1, I generated the “fifo16w16r_2048.v” by “fifo16w16r_2048.xco”, and added it to the project.
I tried the top-level source type both as “ngc/ngo” and “HDL”, added the 3 verilog files in “XEM3010-verilog” as well as the “xem3010.ucf”, and the okLibrary.v plus all the *.ngc files from “FrontPanelHDL\XilinxISE82”.
The project failed when generating the programming file.
The error is “ramtest.v line 37 Illegal redeclaration of ‘fifo16w16r_2048’, module fifo16w16r_2048 compiled, module ramtest compiled, Analysis of ram_test.prj failed”.
What steps shall I take to generate the ramtest.bit file by myself?
In readme.txt, there are some instructions for example of “counter”. But for “Ramtester” there should be another one.
Thanks for your answering!