I have managed to get Chipscope running on my XEM3010 the “old way”-using Core Generator to create an ICON and ILA core, then instantiating them in the top-level verilog file using the templates that Coregen provides.
I cannot get Chipscope to work the “new way”-using Chipscope Core Inserter to generate the cores and do the post_PAR insertion. The ILA will show up in FPGA editor, but I get “Found 0 core units” when I start the Chipscope Analyzer.
I have posted on the Xilinx forum, and tried a slew of suggested fixes. One of the suggestions was to set the Bitgen “FPGA Start-Up Clock” Property to “JTAG Clock” (The default is CCLK)
When I load the bitfile (using the OK API) created with “FPGA Start-Up Clock”, I get:
instead of the usual:
Is there anything about the “okDoneNotHigh” status that might be worth passing along to Xilinx? There are known issues with other devices in the JTAG chain that might be related.