Will Chipscope work over the OpalKelly USB interface, or do I need to run a Xilinx JTAG cable to the JTAG pins on the OpalKelly board (XEM3010 in my case)?
If I use a Xilinx JTAG cable, do I need to uncomment the JTAG pins in the OpalKelly ucf template?
If Chipscope does run over the OpalKelly USB interface, do I need to do anything special in the ISE “Configure Target Device” tool?
You can use Chipscope over the on-board JTAG connections and the Xilinx JTAG cable. It is completely independent from our software and interface.
You do not need to uncomment the JTAG pins in the UCF template. These are provided to allow the FPGA to drive the JTAG pins. For example, the FPGA could be used to program the PROM in this manner. In most applications, however, these pins should just be left unconnected or high-impedance.
I have managed to get Chipscope running on my XEM3010 the “old way”-using Core Generator to create an ICON and ILA core, then instantiating them in the top-level verilog file using the templates that Coregen provides.
I cannot get Chipscope to work the “new way”-using Chipscope Core Inserter to generate the cores and do the post_PAR insertion. The ILA will show up in FPGA editor, but I get “Found 0 core units” when I start the Chipscope Analyzer.
I have posted on the Xilinx forum, and tried a slew of suggested fixes. One of the suggestions was to set the Bitgen “FPGA Start-Up Clock” Property to “JTAG Clock” (The default is CCLK)
When I load the bitfile (using the OK API) created with “FPGA Start-Up Clock”, I get:
okDoneNotHigh
instead of the usual:
okNoError
Is there anything about the “okDoneNotHigh” status that might be worth passing along to Xilinx? There are known issues with other devices in the JTAG chain that might be related.
Hm. Well, when you use FrontPanel to download the bitfile, the bitfile should be configured with CCLK as the startup clock.
When you use JTAG, the Xilinx tools automatically (I think) configure the bitfile for JTAG start clock, so you can generally just leave the setting on CCLK.
okDoneNotHigh just means that, once the FPGA was configured, DONE was expected to be asserted, but it was not. This typically implies a fault with the configuration file in some manner.
Was there some other indication that the configuration file was accepted by the FPGA? (e.g. you configure the LEDs to do something in particular)
The Core Inserter works after upgrading ISE, Chipscope, and IP to SP3.