How to configure multiple fpga device with FP?

@O-K
I am looking at your FMC shuttle card, and wondering about attaching it to a daughtercard of a my own application. This daughtercard would also have a xilinx s6 fpga chip on it, and its jtag port would be in the chain loop with the fpga on the shuttle card. My question is whether I would be able to program the daughterhard fpga through the USB with FP function ConfigureFPGA, and how if possible ? Thanks
H.M.:o

You could not use ConfigureFPGA.

However, you could include configuration logic in your Shuttle FPGA design and pass the configuration through.

Can you elaborate it a little bit ? Thanks

@O-K
I am renewing my request for a little more elaboration on this, just a few more lines please. Thanks
:o

[QUOTE=Opal Kelly Support;3952]You could not use ConfigureFPGA.

However, you could include configuration logic in your Shuttle FPGA design and pass the configuration through.[/QUOTE]

You would need to build a configuration interface into the FPGA. This would not be terribly difficult. Serial configuration of an external FPGA is simply a matter of initiating configuration and providing clock and data. The data would presumably be coming from a Pipe In and would need to be buffered so as not to exceed the maximum transfer rate of this interface. Xilinx publishes a configuration user guide for each generation of its FPGAs.

You could also use a word-wide interface and not require any buffering for USB 2.0 speeds.

Thanks, and it makes sense.
h-m

[QUOTE=Opal Kelly Support;3972]You would need to build a configuration interface into the FPGA. This would not be terribly difficult. Serial configuration of an external FPGA is simply a matter of initiating configuration and providing clock and data. The data would presumably be coming from a Pipe In and would need to be buffered so as not to exceed the maximum transfer rate of this interface. Xilinx publishes a configuration user guide for each generation of its FPGAs.

You could also use a word-wide interface and not require any buffering for USB 2.0 speeds.[/QUOTE]

Got it, and that is essentially to do what xc3sprog does in software in fpga, do that slowly.:p:o

[QUOTE=Opal Kelly Support;3972]You would need to build a configuration interface into the FPGA. This would not be terribly difficult. Serial configuration of an external FPGA is simply a matter of initiating configuration and providing clock and data. The data would presumably be coming from a Pipe In and would need to be buffered so as not to exceed the maximum transfer rate of this interface. Xilinx publishes a configuration user guide for each generation of its FPGAs.

You could also use a word-wide interface and not require any buffering for USB 2.0 speeds.[/QUOTE]

Well, in a sense, yes. But since the FPGA is doing this, it is not done “slowly”.

At USB 2.0 rates, you can do word-wide programming at full speed. Serial rates will require some slowing because you’d be going faster than the FPGA could accept the data.

What would be a good way to read out word by word from a binary .bit file ? Thanks

[QUOTE=Opal Kelly Support;3977]Well, in a sense, yes. But since the FPGA is doing this, it is not done “slowly”.

At USB 2.0 rates, you can do word-wide programming at full speed. Serial rates will require some slowing because you’d be going faster than the FPGA could accept the data.[/QUOTE]