when I do “Implement Design” at ISE Project Navigator to prepared sample i get errors.
The order of action:
file->new project->add detaills of XEM3005.
add source->counters.vhd,xem3005.ucf, oklibrary.vhd->
Synthesize - XST (with warning)->
Implement Design (with errors)
What am i doing wrong? and how can i fix it? what should i do?
Neta–
The README in the Samples folder has this section:
[QUOTE]Step 3: Copy Opal Kelly FrontPanel HDL files
From the FrontPanel installation directory, copy the HDL module files.
For this example, we’ll use the files from XilinxISE10p2. Note that
these files are forward-compatible with newer ISE versions.
- okLibrary.v - Verilog library file
- *.ngc - Pre-compiled FrontPanel HDL modules[/QUOTE]This is also mentioned in the FrontPanel User’s Manual in the HDL Modules section:
[QUOTE]
You should also copy the pre-synthesized files (*.ngc) that you use into your project directory. You do not need to copy module files that you are not using. The .ngc files will then be used by the Xilinx tools during the Translate step in order to completely build the FPGA configuration file.
[/QUOTE]Did you perform this step?