Help using DDR3 RAM and Clock Gen IP With XEM7310

I’m working on a project where I want to use an MIG Xilinx generated IP as my memory controller to interface with the DDR3 RAM and a Clocking Wizard IP to generate two internal clock signals. My project contains a IBUFGDS instance at the top-level which receives my differential clock inputs (200Mhz oscillators on pins W11, W12) and outputs a sys_clk. I would like for my memory controller to receive this internal sys_clk as well as it’s boolean negation (!sys_clk) as it’s differential clock inputs. I followed OKs settings guidelines for generating the controller and even edited the generated RTL for the IP so that DIFF_TERM_SYSCLK is false and therefore the memory controller should not be expecting differential terminations on the clock inputs. Unfortunately I’m still getting two DRC REQP-62 errors when I try to implement my design. These errors basically state that the IBUFG buffers within the memory controller are receiving illegal inputs. Anyone have any advice on how to get around this issue, or possibly have an example where they got OK to interface with the DDR memory? Let me know if you need any further clarification on what I’m asking.