I’m using Xilinx PlanAhead v14.7 on Windows 7 Enterprise.
The part I am programming for is an XC6slx150_fgg484-2, on an XEM6010-LX150. When I elaborate the design, I get this error from PlanAhead:
[EDIF 20-96] Could not resolve non-primitive black box cell ‘okCoreHarness’ instantiated as ‘core0’ [“C:/Users/rosecm1/etc…/FPGA_Mezz_031518_try5.srcs/sources_1/imports/src/okLibrary.vhd”:118]
so the okLibrary.vhd file referenced here has an instantiation of the okCoreHarness:
core0 : okCoreHarness port map(okHC=>okHC, okCH=>okCH, ok1=>ok1, ok2=>ok2);
And it also has a component, in the architecture of okHost, which looks like this:
component okCoreHarness port ( okHC : in std_logic_vector(24 downto 0); okCH : out std_logic_vector(20 downto 0); ok1 : out std_logic_vector(30 downto 0); ok2 : in std_logic_vector(16 downto 0)); end component;
The signals called out in the port map of the instantiation are the same types and sizes of the ports on the component.
The PlanAhead tool includes in its list of sources, a set of .ngc files, including one for okCoreHarness.ngc. This file is ascii, 286K long, and illegible to me, other than this header:
XILINX-XDB 0.1 STUB 0.1 ASCII
Is there something I’m doing wrong? How can I debug this? Any help or suggestions are appreciated!