Future board design suggestions


Is there any chance of having these in future board designs? :slight_smile:

  1. Use the new Cypress FX2LP for lower power.

  2. Modify the connectivity between FX2 and FPGA so that the FX2 can operate in slave fifo mode. The FPGA needs to drive SLWR/SLRD, FIFOADR, etc. This would maximize data transfer rates (up to 40MB/s with some USB 2.0 chipsets).



Ooops… I should have posted this in the “Suggestions” section.




The FX2LP has been built onto a handful of XEM3001s for our testing. It will be incorporated into our next lot build in a couple months. Availability has been the limiting factor until now. Results show that current goes from 270 mA (unconfigured FPGA) to about 110 mA – leaving a fair bit more for FPGA consumption.

We have also considered offering an alternate firmware with features such as you describe. It isn’t clear on when/if that update will be available or how it will interact with the current API. We’ll post any updates here to the forums and keep you in mind for any beta testing.

Thanks for the suggestion!



i am also interested in the FX2LP version. And also in the SDRAM add-on.

Do you have release dates?

Best regards,




New stock with the FX2LP devices should be arriving next week. However, we will deplete our current FX2 stock before announcing the FX2LP on devices.

The SDRAM module should be available early in September.