Is there any chance of having these in future board designs?
Use the new Cypress FX2LP for lower power.
Modify the connectivity between FX2 and FPGA so that the FX2 can operate in slave fifo mode. The FPGA needs to drive SLWR/SLRD, FIFOADR, etc. This would maximize data transfer rates (up to 40MB/s with some USB 2.0 chipsets).