My understanding of okHostCalls.v is that it mimics the signals coming into the FPGA. That means, it is behaving like the external USB controller.
So, I created a module that includes the file okHostCalls.v
I then connect the ports on this module I created to my FPGA top file.
When I compile, the compiler complains that “BlockDelayStates” is not declared, which is true.
At this moment, I start to think that my understanding of okHostCalls is wrong.
My question is …
Where do I include okHostCalls.v? If it is to be included on the same level as where okHost.v is instantiated, then “BlockDelayStates” is still not declared.
Basically, my question is, how do I use okHostCalls.v
The goal of the simulation is actually to simulate the signals your HDL would see from the endpoints. There is no effort to simulate the actual signals from the host to the host interface in the FPGA.
Have you reviewed the section titled “FrontPanel Host Simulation” in the FrontPanel User’s Manual. It gives a fairly in-depth discussion of test bench setup. Additionally, the DES Sample ships with a simulation version you can use as a reference.
The goal of the simulation is actually to simulate the signals your HDL would see from the endpoints. There is no effort to simulate the actual signals from the host to the host interface in the FPGA.
Have you reviewed the section titled “FrontPanel Host Simulation” in the FrontPanel User’s Manual. It gives a fairly in-depth discussion of test bench setup. Additionally, the DES Sample ships with a simulation version you can use as a reference.[/QUOTE]
Thanks for pointing out to the example in DES. The example help me fill the gap of what else I need to do after including the okHostCalls.v.
The problem I had was that I have 2 okHost in my “system”. I am simulating two OK boards with both FPGA talking to each other. So, what I need to create one module for each interface to each okHost.
Ah. That’s a scenario we haven’t really run through the simulation. If, after you’ve worked this exercise, you have any suggestions on how we could improve the simulation setup, please send an email to support!
In my opinion. The best thing to do is to provide a module that is self contained. The ports of this module connects to the FPGA top’s host bus interface.
So, all we need to do is to instantiate this module.
My 2c.
BTW, I just realized that in the DES example. In the XEM6006-Verilog directory, desktop.v contains a port called hi_aa. However in Simulation-USB-Verilog, that port is missing. Is there a reason why?
DES/XEM6006-Verilog/desktop.v (contains hi_aa)
DES/Simulation-USB-Verilog/desktop.v (no hi_aa)