Hello,
I’ve been testing the FrontPanel Host Simulation HDL. Even with the LFSR example simulation design that the FrontPanel IP core can generate, I see some unexpected behavior:
-
In both behavioral and post-synthesis simulation, the signal
okUH[0]
(okClk) always has a 10 ns period (100 MHz). -
According to the documentation, the FrontPanel clock should be 100.8 MHz.
-
I tried changing the
okHostInterface
parameters (Tsys_clk, BlockDelayStates, ReadyCheckDelay, etc.), but they had no effect on the clock frequency. -
The only time I noticed a change was when I switched the
timescale
from1ns/1ps
to1ps/1ps
. At that point, the clock period dropped to about 10 ps, which clearly isn’t correct either.
So my question is:
-
Is the simulation clock frequency fixed at 100 MHz by default?
-
Does the
FrontPanelReset
task set the simulation clock to 100 MHz regardless of user parameters? -
If not, what’s the proper way to adjust the simulation clock to 100.8 MHz?
Thanks in advance!