I’ve just tried this on my laptop (P4-1.4GHz/XP Pro) and my home desktop machine (Athlon-XP 2800+/Win2k). The laptop didn’t show a single instance of the FPGA failing to configure, and the desktop only showed it once (loading the counter bit file, the LEDs didn’t start to count) - this was not reproducible.
Experience (about 10 years of professional Xilinx use) tells me that if the config doesn’t work on a fast machine, it is usually because one of the more subtle configuration parameters is being violated.
(forgive me if I am teaching grannies to suck eggs here!)
Are you waiting long enough after PROG_B goes high, if you are not monitoring the INIT_B pin (some circuits don’t).
Are you waiting long enough after the config has been clocked in, and before the start-up cycle? The datasheet doesn’t show this, but a short wait (100us or so) is often helpful.
If you are clocking CCLK faster than 66MHz, are you monitoring the BUSY pin?