Front Panel registerbridge speeds and timing

In the USB3 version of the frontpanel read and write registers are possible using the rgeisterbridge
I may have missed it, but is there an indication about the speed of the read and write registers for these readreg / writereg and readregs/writeregs calls
The frontpanel-UM registerbridge timing picture makes one assume that a few readregs / writeregs will be executed on consequentive okClk cycles.
Is this just an example or can I assume this happens (up to ?? reads/writes )