FPGA Pin map for on-board clocks?

I tried looking up in the datasheet of ZEM4310. I would like to know which FPGA pins are connected to the on-board 50 MHz and 100.8 MHz from the host interface.

From looking at zem4310.qsf, there is this A12 pin which is assigned to sys_clk. Is this 50 MHz or 100.8 MHz?

Should this information be included in the ZEM4310 datasheet/manual?

Hi thetorque,

The sys_clk is an on-board oscillator that, on the ZEM4310, operates at 50MHz. It is separate from the host interface clock, which operates at 100.8 MHz. In zem4310.qsf, the host interface clock is called “hi_clk” and is connected to the G1 pin.


Hi, I’m starting a new project with the ZEM4310 board. I first anted to measure the sys_clk and the ok_Clk and for this reason I mapped them on two different pins of the breakout board. I’ve correctly measured 50MHz and 100.8MHz for the two clocks. I’ve then checked the ZEM4310.qsf file and I’ve found that the sys_clk is mapped to PIN_A12, but there is no trace of neither “ok_clk” nor “hi_clk” signals in the same file. Is this correct?