FPGA I/O pin assignments in the manual

Poking around the FPGA pin use on the XEM3005, I came up with the following three observations.

  1. The following pins on JP3 don’t have accessible counterpart differential pins. The counterpart pins are respectively connected to the LED, SPI, and SDRAM. The XEM3005 manual should include a notation that these pins cannot be used for differential input or output so that a user doesn’t go searching the table for the other pin.

JP3-26 P16 IO_L02P_1
JP3-30 M16 IO_L04N_1
JP3-64 B11 IO_L05N_0

  1. The JP3 table does not list the XC3S1200E pin for JP3-54 E16. It is I/O_L17N_1, which is the differential counterpart of JP3-55 E13 I/O_L17P_1. I tested these as a differential output pair on the XEM3005 and they work appropriately, but the function of JP3-54 isn’t clear from the table in the manual.

  2. Finally, FPGA I/O pins B3, M10, P4, R9, R14, and T10 are unaccounted for in the XEM3005 manual. Are these unconnected? Just curious.


  1. The XEM3005 was not designed for differential usage. While this is possible on some of the pins, the routing was not specifically designed for this as it was on the XEM3010.

  2. Thanks for pointing this out. This is a mistake in the table and has been fixed.

  3. These are necessary connections for the boot and configuration of the FPGA. They are connected, but not available for general use.

  1. I’ll stand by my suggestion of a notation for these pins in the manual. The manual is silent on the subject of differential signalling and does not discourage it. While you say that it is possible on some pins, it is really possible on 75% of the I/O pins available to the user. But not these, despite their labels.

  2. As I expected. Thanks for satisfying my curiosity.


We’ll consider your suggestion. You say that it is “possible on 75% of the I/O pins available…” What do you mean that it is possible on them, but not these despite their labels?

First, differential transmission/reception is only possible if both pins of a pair are available. So this limits you to only complete pairs which we have made available.

Second, referring to the Spartan-3E materials, LVDS transmitting is only possible on pairs where the bank voltage is selectable to 2.5v. LVDS reception (according to Xilinx) is possible on banks with 2.5v or 3.3v.

So, of those remaining, why is diff. signaling not possible despite their labels?

I mention this because we have a general conflict regarding our documentation. We need to document our products as best as possible for customers to use them, but we merely provide a framework through which the customer is able to apply the far more complicated FPGA device. So, while trying to provide concise documentation for our products, we are trying to avoid repeating Xilinx documentation.

I feel comfortable mentioning that we do not provide differential pair matching or impedance control on the XEM3005, and will have that added to the documentation. But saying that you cannot use a pin for differential signaling because its pair is not available seems, to me, redundant.


I just checked our documentation and found this line (page 14):

— Begin quote from ____

Note that, while these lengths may be used to help equalize lengths for certain applications (like LVDS pair matching), the XEM3005 is not an impedance-controlled PCB and was not designed specifically for LVDS use.

— End quote

Is there additional text you think should be added?

OK. I’ll back off on this. I’m a bit sorry for starting the thread, but I want to explain my thinking (There actually was some.) before going away.

It is possible to create instantiations of OBUFDS and IBUFDS buffers on 3.3 banks and I was thinking that I had created a LVDS_33 output or input. Some Xilinx documents refer to LVDS_33 as the default differential IOSTANDARD. Now that I’ve studied the Xilinx documents again, I see that this is an I/O standard for the Spartan-3A but not the Spartan-3E. My mistake.

However, I CAN instantiate OBUFDS on a 3.3V bank without specifying the IOSTANDARD and when I do I get a working differential output on a pair of pins on the XEM3005. What have I really created in this case? Why shouldn’t I use this as a differential output? Is this dangerous to the FPGA? The fact that these worked was why I didn’t notice the limitations in the Xilinx docs. Bad practice on my part but it leaves me wondering.

I understand that the XEM3005 was not specifically designed to support LVDS, but I thought that this was an issue only if the performance envelope is being pushed.

As for my 75% number, the I/O pins on JP3 and JP4 have the following breakdown (unless I counted wrong):

24 pins, dedicated inputs, single ended
12 pins, dedicated inputs, in 6 differential pairs (xyz_p and xyz_n both on the connector)
2 pins, input/outputs, single ended
62 pins, input/outputs, in 31 differential pairs
3 pins, input/outputs, without a differential pair on JP3

Therefore, 77 pins out of 103 are members of a differential pair. That was my math for the 75% number. That may be meaningless math given the above discussion, but that’s what I was thinking.

I wasn’t suggesting that the manual state that differential signaling is possible only if both pins are available (which is indeed redundant), but that there could be a asterisk of something at those pins for which the mate is not in the table. That would avoid someone picking a pin, then searching the table for a mate which is not in the table. But maybe that would encourage differential use where it is not encouraged.

Thanks Bob, for the discussion. Our documentation shouldn’t be created in a vacuum and this is the best way to assure that it addresses the points that you want to hear about and not only the ones we want to tell you about!

I’m not sure exactly what you created with the OBUFDS. Their software is complex and supports a myriad of configurations, so I wouldn’t be surprised if this is a bug. It may also be a funky supported configuration.

Our initial release of the XEM3005 documentation did not include the trace lengths – these can be used to do pair length matching for diff. signaling. We added this to support some requests. I can add a note with the LVDS note that not all signals are provided as matching pairs. I think, in context there, it will not encourage diff. use of the board.

I know now why ISE accepted my instantiation of the LVDS driver, but I don’t understand what I should have been doing differently. The ISE pin report indicates that the tool thinks that all of the supply voltages are 2.5 V, so it happily provided me with what it thought were LVDS_25 outputs. ISE doesn’t know that the VCCO values are really 3.3 V (they are, aren’t they?). I cannot find where I was supposed to indicate the actual voltages. Can someone tell me where (in ISE or PACE or somewhere else) these voltages are supposed to be defined for a given project? I’ve searched unsuccessfully in the documents I have and on the web. I’m using the free, downloadable tools from Xilinx.


The .ucf file specifies the voltages for the pins.

Technically, our UCF files should probably include specifications for 3.3v. Since, for LVCMOS I/O, there’s no configuration difference between 3.3v and 2.5v, we left this off for clarity.

The UCF file also specifies the drive strength per pin. Again, technically, all such parameters should be diligently provided by the designer to optimize performance and power consumption.

You can look at the pads report to see what parameters ISE has defaulted to.