[QUOTE=Opal Kelly Support;2674]@Brent–
We suggest configuring the constraints to ignore paths through the host interface and endpoint modules. You should be able
to simply ignore paths dependent upon ti_clk unless you use that in your design.
The sheer volume of warnings that Xilinx tools emit is bothersome. It would certainly help if they could reduce those to at
least warnings of relevance. Most of the warnings are for pretty petty matters.
I don’t think that is a sensible solution. I assume you mean applying TIGs to ignore timing. This will have the effect of releasing the ‘ti_clk’ from its timing constraint altogether and then the design may or may not compile to a correctly timed build.
Also, yes it is used in my design for various management issues, eg. clock activity monitoring.
It is regarded as good design practice to make sure one has a 100% constrained design (and I’ve had my butt kicked when I’ve missed constraints out before)
Yes, I understand that they are just functional simulation models, but I just need the relationship of the external ‘ti_clk’ to the ‘ok2’ bus clock in order to constrain it. I can get the set-up and hold timings from the Cypress USB Microcontroller data sheet.