FPGA Host Interface Timing Constraints

Suggestions
1

Is it possible to obtain some information on the Host Interface and wire/pipe/trigger blocks used in the FPGA, with regards to structure and clocks.

Specifically, I am using the XEM3005 board and would like to add timing constraints for these blocks.

I assumed (wrongly) that the I/O would be based on hi_in[0] (ti_clk), but now realize that they are all clocked by ok1[24].

Any help would be appreciated.

Best Regards & Seasons Greetings,

Brent Hayhoe

2

Brent-- We don’t release any further details about the host interface or endpoint modules.

However, we have yet to find a situation that requires constraints on these signals. The host interface runs at a frequency of 48 MHz which is pretty low by Spartan-3 standards.

Have you found that you need to setup constraints?

3

Thanks for the reply.

No, it’s not so much that I need to constrain the interface to meet timing, but rather to help clear up the synthesis reports file such that I can easily spot other parts that are unconstrained. I have parts of the design running up at 300MHz, close to the limit for the 3E part that I’m using and these really do need constraining properly. I have made a reasonable estimate for the ‘set-up’ and ‘hold’ timings for the SDRAM and this builds and runs correctly without any fixed phase shift in it’s DCM (based on your RAMTester example)

I could make a reasonable good guess from my simulations as to how the blocks are working; it would just be nice to know that it is the correct guess!

Cheers,

Brent.

4

@Brent–

We suggest configuring the constraints to ignore paths through the host interface and endpoint modules. You should be able to simply ignore paths dependent upon ti_clk unless you use that in your design.

The sheer volume of warnings that Xilinx tools emit is bothersome. It would certainly help if they could reduce those to at least warnings of relevance. Most of the warnings are for pretty petty matters.

Also note that the host interface simulations aren’t intended to assist with timing. The signals are contrived to produce the simulation results and are not a valid representation of the actual signals used in the design.

5

[QUOTE=Opal Kelly Support;2674]@Brent–

We suggest configuring the constraints to ignore paths through the host interface and endpoint modules. You should be able
to simply ignore paths dependent upon ti_clk unless you use that in your design.

The sheer volume of warnings that Xilinx tools emit is bothersome. It would certainly help if they could reduce those to at
least warnings of relevance. Most of the warnings are for pretty petty matters.
[/QUOTE]

I don’t think that is a sensible solution. I assume you mean applying TIGs to ignore timing. This will have the effect of releasing the ‘ti_clk’ from its timing constraint altogether and then the design may or may not compile to a correctly timed build.

Also, yes it is used in my design for various management issues, eg. clock activity monitoring.

It is regarded as good design practice to make sure one has a 100% constrained design (and I’ve had my butt kicked when I’ve missed constraints out before)

Yes, I understand that they are just functional simulation models, but I just need the relationship of the external ‘ti_clk’ to the ‘ok2’ bus clock in order to constrain it. I can get the set-up and hold timings from the Cypress USB Microcontroller data sheet.