I have a 3010 board with a 1500 on it.
I have been successfully able to take the first.ise project, move it to another directory, rename it, make a change to the verilog source code to bring the clock out on a pin, change the UCF file to bring the clock to a known pin, create a bit file, load it with front panel, and see that the clock does come out on the pin I specified.
However, the above solution is klunky for me and only seems to work when I make the new directory in a sub directory of “first”.
I tried simply to create a new project from scratch and I end up with errors during place and route. Does any have any ideas from the below place and route report ?
I must not be linking in all the files or not setting an appropritte project option.
To create the project, I put the UCF, and v file in a new directory, rename them, open project navigator 7.1, and create a project including first.v, the UCF file, and the okLibrary.v file in the C:\Program Files\Opal Kelly\FrontPanel\FrontPanelHDL\XilinxISE71_v2 directory.
Any help would be appreciatted.
Thanks,
Randy
Started process “Synthesize”.
=========================================================================
-
HDL Compilation *
=========================================================================
Compiling verilog file “okLibrary.v”
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Module compiled
Compiling verilog file “First_6.v”
Module compiled
No errors in compilation
Analysis of file succeeded.
=========================================================================
-
HDL Analysis *
=========================================================================
Analyzing top module .
Module is correct for synthesis.
Analyzing module .
Module is correct for synthesis.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
Set user-defined property "DRIVE = 12" for instance in unit .
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
Set user-defined property "IFD_DELAY_VALUE = AUTO" for
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
Set user-defined property "SLEW = SLOW" for instance in unit .
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
Set user-defined property "DRIVE = 12" for instance in unit .
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit .
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
Set user-defined property "SLEW = SLOW" for instance in unit .
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
Set user-defined property "DRIVE = 12" for instance in unit .
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit .
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
Set user-defined property "SLEW = SLOW" for instance in unit .
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
Set user-defined property "DRIVE = 12" for instance in unit .
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit .
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
Set user-defined property "SLEW = SLOW" for instance in unit .
Analyzing module .
Generating a Black Box for module .
Analyzing module .
Generating a Black Box for module .
Analyzing module .
Generating a Black Box for module .
=========================================================================
-
HDL Synthesis *
=========================================================================
Synthesizing Unit .
Related source file is “okLibrary.v”.
Unit synthesized.
Synthesizing Unit .
Related source file is “First_6.v”.
WARNING:Xst:646 - Signal > is assigned but never used.
Found 1-bit tristate buffer for signal .
Found 1-bit tristate buffer for signal .
Found 16-bit adder for signal .
Summary:
inferred 1 Adder/Subtractor(s).
inferred 2 Tristate(s).
Unit synthesized.
=========================================================================
-
Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference …
Advanced multiplier inference …
Advanced Registered AddSub inference …
Dynamic shift register inference …
=========================================================================
HDL Synthesis Report
Macro Statistics
Adders/Subtractors : 1
16-bit adder : 1
Tristates : 2
1-bit tristate buffer : 2
=========================================================================
=========================================================================
-
Low Level Synthesis *
=========================================================================
Optimizing unit …
Loading device for application Rf_Device from file ‘3s1500.nph’ in environment C:/Xilinx.
Mapping all equations…
WARNING:Xst:2036 - Inserting OBUF on port driven by black box . Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port driven by black box . Possible simulation mismatch.
Building and optimizing final netlist …
Found area constraint ratio of 100 (+ 5) on block First, actual ratio is 0.
=========================================================================
-
Final Report *
=========================================================================
Device utilization summary:
Selected Device : 3s1500fg320-4
Number of Slices: 8 out of 13312 0%
Number of 4 input LUTs: 16 out of 26624 0%
Number of bonded IOBs: 38 out of 221 17%
Number of GCLKs: 1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
No clock signals found in this design
Timing Summary:
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.797ns
=========================================================================
Started process “Translate”.
Command Line: ngdbuild -intstyle ise -dd c:\my_designs\first_one\xilinx4/_ngo
-nt timestamp -uc xem3010_6.ucf -p xc3s1500-fg320-4 First.ngc First.ngd
Reading NGO file ‘C:/my_designs/first_one/xilinx4/First.ngc’ …
Applying constraints in “xem3010_6.ucf” to the design…
Checking timing specifications …
Checking expanded design …
ERROR:NgdBuild:604 - logical block ‘ep00’ with type ‘okWireIn’ could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol ‘okWireIn’ is not supported in
target ‘spartan3’.
ERROR:NgdBuild:604 - logical block ‘ep01’ with type ‘okWireIn’ could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol ‘okWireIn’ is not supported in
target ‘spartan3’.
ERROR:NgdBuild:604 - logical block ‘ep02’ with type ‘okWireIn’ could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol ‘okWireIn’ is not supported in
target ‘spartan3’.