FIFO Management

I am having a problem with reading from the FIFO’s using pipes. My FIFO’s 2048 big and 16 wide and I am writing to it at about 100 MHz. The problem is that the computer is not reading from the FIFO fast enough at its speed of 48 MHz to remove the bytes from the FIFO and make space for the incoming bytes. Does anyone have a suggestion of how I can manage this because my problem is that I have too many bytes to read back so no matter how big I make the FIFO I will always have this problem. If possible I would like to find a way to manage this interaction. The only solution I can think of is to create a handshaking between the reading of the FIFO and writing to the FIFO but I would rather not interrupt the process of writing to the FIFO.

To clarify, you’re writing data to the FIFO at a sustained rate of 200 MBytes/sec and you want to read it out via USB which tops out at maybe 38 MBytes/sec?

Yes and the amount of data that I am writing to the FIFO is greater than the actual size of the FIFO, the designers of the ramtester were able to accomplish this goal and my code is similar however, not accomplishing the same goal.

Raphael - what you’re requesting is simply impossible unless you’re able to compress the data you’re sending by over 5:1.

RAMTester does not do this. The PC reads at the top rate of the USB which is around 35MB/s or so, depending on the computer. The logic in RAMTester just keeps the FIFO full enough so that a USB read won’t underflow the FIFO.

When the PC writes at the top rate of the USB, the logic in RAMTester performs SDRAM writes to make sure that the FIFO does not overflow.

The SDRAM can operate at up to about 250 MB/sec, but it certainly isn’t doing this at a sustained rate when transferring over USB.

Ok so I am a little confused so could you please explain something to me. The Ramtester reads 8 MB of data in 4 clusters to read the total 32 MB on the SDRAM. It uses a 2 MB fifo and it does not overflow (write over locations that have not been read from the fifo yet). I have been studying that code to see how it is able to not run into an overflow condition since the SDRAM writes faster than the computer can read. Could you explain this to me?

See the N_IDLE state logic. It’s even commented:

[CODE] n_idle: begin
staten t engage the SDRAM.

Ok I understand, I was not recognizing/remembering the fact that a set number of reads are being performed (512) so it is able to read the whole memory by continuously reading then dumping, reading then dumping and it will not read unless as you said there is space in the FIFO. Thank you for your help.