Anybody hooked up an Async FIFO to the new okBTPipeOut? The old okBufferedPipeOut was built in. I’m especially curious about how to hook in the Read side (Host Interface side) clock. I’m wanting to use a circular buffer concept. Sharing of previous experience and ideas in this 1.4 mapping to 3.0 area are appreciated.
kdriskill–
The 1.4 BufferedPipes used a FIFO that was built from a Xilinx app note. They were included because, at the time, the Xilinx FIFO Core Generator was not included with the free Xilinx ISE tools.
Jump ahead a couple years and Xilinx now includes the core generator with their free package. The FIFO Core is far more flexible and efficient. Therefore, we just decided to get rid of the BufferedPipes.
The timing is compatible. Just create a FIFO core and hook it up to the okPipe or okBTPipe.
Thanks, but I still have the question about which okBTPipeOut signals are available for me to hook up to the Read side of the FIFO. e.g. the read side clock needs to be: TI_CLK which is: hi_in(?) the ready signal is mapped to hi_in(?) etc…
You should not be using the hi_in signals at all. Use the signals available on the target module (EP_READY) and the host interface module (TI_CLK).
The host interface provides TI_CLK which is the clock you should use to synchronize anything with the endpoints you use. That is the same clock used by the endpoints.
Does this clear things up?
okSupport,
I think so. I just need to be sure that TI_CLK is routed over to the module which instantiates okBTPipeOut and use TI_CLK as the Read clock for the fifo that I will build there. By the way, please refer to an earlier post I have made concerning pinout questions regarding how hi_in and hi_out will map to Xilinx LOCs which were mapped some time ago to an older FP1.4 design. I currently plan on using FP3.0 to take advantage of the BTPipes and will let you know how that goes.
Regards,