External RAM

  1. I would like to transfer a 16 bit x N array into the external 16MB DRAM using C++. How do I know where to send the data.

  2. I would then like to pipe this data to the output pins

  3. Is there any documentation on the external DRAM?

Any help would be greatly appreciated.



Well Cody this is not so simple as you think. DRAM needs refreshes and precharge that you must incorporate in PFGA core (C++ wont do you any good). It would be very nice to get FPGA DRAM core from OpalKelly and reference DRAM board. It would be also very nice that core is customizable to suit almost any DRAM.
For documentation on external DRAM you can go to
and download datasheet of appropriate DRAM.


Guru- We’re getting an SDRAM/SSRAM board ready for production. Cody actually has a pre-production one. A reference controller is also in the works, but I find that business somewhat silly. For good performance, an SDRAM controller should be optimized for the particular transfers that will be taking place. Otherwise, one ends up with a controller to control the controller.

Your input is welcome – what would you want the reference design to do?


Actually I already build a board which has been built for 2x128Mbit DRAM. When I studied the datasheet I quit the thought for memory controller core implementation. The memory core you are developing is probably not burst oriented. I have CMOS imaging sensor on board with 66MHz parallel interface. Is your board capable of this speed? If it is I would be glad to get the memory interface core.



Hi Guru-

We currently don’t have a memory core available for public use. However, I wouldn’t be intimidated by the datasheets. It really isn’t too complicated to get a simple controller that just handles page writes / page reads. In fact, it is -easier- to handle only burst transfers.

Our memory cores and the board handle speeds up to 133 MHz without problems.

I’ll give you a hint – use a FIFO (1024-word or so) to buffer data coming from either the USB side or the camera interface. When the buffer gets to be half full, signal your DRAM controller to make a full-page (512-words in many SDRAMs) transfer. Likewise, you can use the half-empty signal to move data in the other direction.

If you keep transfer lengths restricted to multiples of the DRAM page, you can make a controller than only deals with page bursts. Life becomes a lot easier!!