Expecting endmodule error

Okay, I am just starting to program in verilog and I don’t understand this error at all. Can you help me?

Here is code:

module testingIf(in, out);
input [3:0] in;
output [3:0] out;

reg x[3:0];

assign x = 1'b0;

if(x[0] == 1'b0)
  x[0] t understand and I have tried everything I can think of. This is also a smaller example of what the larger problem is but the error is just the same.

Thank you for your time.

For starters, your “if” conditional needs to be contained in a begin/end block.


Lots of things look odd about this code. First, do you really mean to declare reg x[3:0] or do you mean reg [3:0] x? You assign x to the output so I assume that you mean for x to be four bits wide as is out, rather than as an array of one-bit values. Second, do you really want to assign x[0] to 1’b0? The assign is like a hard wire, but then you want to change the value within your “if” statement. A register value can be assigned within the declaration. Third, what is going to clock this process? This looks like it was expected to act like a procedural function in which x[0] would change value on each call to the function. Should there be a clock edge test for execution of the “if”?

Those things may not explain your error, but maybe it was all too confusing to the synthesizer.