Hi,
The Buttons to light the LEDs doesn´t work too. the verilog code and the .ucf File are looking like the lines bellow.
Verilog:
default_nettype none
timescale 1ns / 1ps
module First(
input wire [4:0] okUH,
output wire [2:0] okHU,
inout wire [31:0] okUHU,
inout wire [3:0] okAA,
input wire sys_clkn,
input wire sys_clkp,
output wire [7:0] led
);
// Clock
wire sys_clk;
IBUFGDS osc_clk( .O(sys_clk), .I(sys_clkp), .IB(sys_clkn) );
// Target interface bus:
wire okClk;
wire [112:0] okHE;
wire [64:0] okEH;
// Endpoint connections:
wire [31:0] ep00wire;
wire [31:0] ep01wire;
wire [31:0] ep02wire;
wire [31:0] ep20wire;
reg [31:0] ep21wire;
assign led = ~ep00wire[7:0];
assign ep20wire = {32’h0000};
always @(posedge sys_clk) ep21wire <= ep01wire + ep02wire;
// Instantiate the okHost and connect endpoints.
wire [65*2-1:0] okEHx;
okHost okHI(
.okUH(okUH),
.okHU(okHU),
.okUHU(okUHU),
.okAA(okAA),
.okClk(okClk),
.okHE(okHE),
.okEH(okEH)
);
okWireOR # (.N(2)) wireOR (okEH, okEHx);
okWireIn ep00 (.okHE(okHE), .ep_addr(8’h00), .ep_dataout(ep00wire));
okWireIn ep01 (.okHE(okHE), .ep_addr(8’h01), .ep_dataout(ep01wire));
okWireIn ep02 (.okHE(okHE), .ep_addr(8’h02), .ep_dataout(ep02wire));
okWireOut ep20 (.okHE(okHE), .okEH(okEHx[ 065 +: 65 ]), .ep_addr(8’h20), .ep_datain(ep20wire));
okWireOut ep21 (.okHE(okHE), .okEH(okEHx[ 165 +: 65 ]), .ep_addr(8’h21), .ep_datain(ep21wire));
endmodule
.ucf File:
############################################################################
XEM6310 - Xilinx constraints file
Pin mappings for the XEM6310. Use this as a template and comment out
the pins that are not used in your design. (By default, map will fail
if this file contains constraints for signals not in your design).
Copyright © 2004-2010 Opal Kelly Incorporated
Rev Date
############################################################################
CONFIG VCCAUX = “3.3”; //Required for Spartan-6
NET “okUH[0]” TNM_NET = “okHostClk”;
TIMESPEC “TS_okHostClk” = PERIOD “okHostClk” 9.92 ns HIGH 50%;
NET “okUHU[*]” TNM = “okHostINOUT_grp”;
TIMEGRP “okHostINOUT_grp” OFFSET = IN 2 ns VALID 4 ns BEFORE “okUH[0]” RISING;
TIMEGRP “okHostINOUT_grp” OFFSET = OUT 8 ns AFTER “okUH[0]” RISING;
NET “okHU[2]” TNM = “okHostOUT_grp”;
NET “okHU[1]” TNM = “okHostOUT_grp”;
NET “okHU[0]” TNM = “okHostOUT_grp”;
TIMEGRP “okHostOUT_grp” OFFSET = OUT 8 ns AFTER “okUH[0]” RISING;
NET “okUH[4]” TNM = “okHostIN_grp”;
NET “okUH[3]” TNM = “okHostIN_grp”;
NET “okUH[2]” TNM = “okHostIN_grp”;
NET “okUH[1]” TNM = “okHostIN_grp”;
TIMEGRP “okHostIN_grp” OFFSET = IN 2 ns VALID 2 ns BEFORE “okUH[0]” RISING;
############################################################################
System Clocks
############################################################################
NET “sys_clkp” LOC=Y11 | IOSTANDARD=LVDS_25;
NET “sys_clkn” LOC=AB11 | IOSTANDARD=LVDS_25;
NET “sys_clkp” TNM_NET = “okSysClk”;
TIMESPEC “TS_okSysClk” = PERIOD “okSysClk” 10 ns HIGH 50%;
############################################################################
FrontPanel Host Interface
############################################################################
NET “okHU[0]” LOC=“AA8” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okHU[1]” LOC=“U10” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okHU[2]” LOC=“AB5” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUH[0]” LOC=“Y12” | IOSTANDARD=“LVCMOS18”;
NET “okUH[1]” LOC=“AA4” | IOSTANDARD=“LVCMOS18”;
NET “okUH[2]” LOC=“AB3” | IOSTANDARD=“LVCMOS18”;
NET “okUH[3]” LOC=“Y6” | IOSTANDARD=“LVCMOS18”;
NET “okUH[4]” LOC=“AB21” | IOSTANDARD=“LVCMOS18”;
NET “okUHU<0>” LOC=“AB12” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<1>” LOC=“AA12” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<2>” LOC=“Y13” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<3>” LOC=“AB18” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<4>” LOC=“AA18” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<5>” LOC=“V15” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<6>” LOC=“AB2” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<7>” LOC=“AA2” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<8>” LOC=“Y7” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<9>” LOC=“Y4” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<10>” LOC=“W4” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<11>” LOC=“AB6” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<12>” LOC=“AA6” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<13>” LOC=“U13” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<14>” LOC=“U14” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<15>” LOC=“AA20” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<16>” LOC=“T16” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<17>” LOC=“AA10” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<18>” LOC=“U16” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<19>” LOC=“Y15” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<20>” LOC=“R15” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<21>” LOC=“U17” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<22>” LOC=“AA14” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<23>” LOC=“T15” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<24>” LOC=“T10” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<25>” LOC=“Y17” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<26>” LOC=“AA16” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<27>” LOC=“R16” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<28>” LOC=“V9” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<29>” LOC=“AB15” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<30>” LOC=“Y5” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okUHU<31>” LOC=“U8” | IOSTANDARD=“LVCMOS18” | SLEW=“FAST”;
NET “okAA” LOC=“W11” | IOSTANDARD=“LVCMOS18”;
############################################################################
Peripherals
############################################################################
LEDs
NET “led[0]” LOC=“V19” | IOSTANDARD=LVCMOS18;
NET “led[1]” LOC=“V18” | IOSTANDARD=LVCMOS18;
NET “led[2]” LOC=“Y19” | IOSTANDARD=LVCMOS18;
NET “led[3]” LOC=“AB14” | IOSTANDARD=LVCMOS18;
NET “led[4]” LOC=“AB19” | IOSTANDARD=LVCMOS18;
NET “led[5]” LOC=“AB17” | IOSTANDARD=LVCMOS18;
NET “led[6]” LOC=“AB16” | IOSTANDARD=LVCMOS18;
NET “led[7]” LOC=“AB10” | IOSTANDARD=LVCMOS18;