Hello, I have a big problem.
I changed from xem6010 to xem6310.
When using xem6010, I used FIFO_16bit_dual_port_FWFT and FIFO_16bit_dual_port which have 16bit din and 16bit dout.
But, changing from usb2.0 to usb3.0, I had to use 32bit pipe and 32bit FIFO.
So, now my FIFO_32bit_dual_port_FWFT has 32bit din and 16bit dout and my FIFO_16bit_dual_port has 16bit din and 32bit dout. Below is the code.
module OK_WB_Bridge(
input wire [112:0] okHE,
output wire [64:0] okEH,
input wire okClk,
input wire clk_i,
input wire rst_i,
input wire stb_i,
input wire [7:0] adr_i,
input wire we_i,
input wire [31:0] dat_i,
output reg [31:0] dat_o
);
// Wire declarations
wire OKfifowrite;
wire OKfiforead;
wire [31:0] OKdatain;
wire [31:0] OKdataout;
wire [15:0] OK_rec_dat;
wire n_fifo_em;
wire fifoem;
wire fifofull1;
wire fifofull2;
wire [65*2-1:0] okEHx;
okWireOR # (.N(2)) wireOR (okEH, okEHx);
//Circuit behavior
always @(*) begin
if(adr_i == 0) begin
dat_o = {15'b0, ~n_fifo_em, OK_rec_dat[7:0], OK_rec_dat[15:8]};
end else begin
dat_o = {31'b0, fifofull2};
end
end
FIFO_32bit_dual_port_FWFT fifo_in (
.rst(rst_i), // input rst
.wr_clk(okClk), // input wr_clk
.rd_clk(clk_i), // input rd_clk
.din(OKdatain), // input [31 : 0] din
.wr_en(OKfifowrite), // input wr_en
.rd_en(stb_i & ~we_i & (adr_i == 0)), // input rd_en
.dout(OK_rec_dat), // output [15 : 0] dout
.full(fifofull1), // output full
.empty(n_fifo_em) // output empty
);
FIFO_32bit_dual_port fifo_out (
.rst(rst_i), // input rst
.wr_clk(clk_i), // input wr_clk
.rd_clk(okClk), // input rd_clk
.din({dat_i[7:0], dat_i[15:8]}), // input [15 : 0] din
.wr_en(stb_i & we_i), // input wr_en
.rd_en(OKfiforead), // input rd_en
.dout(OKdataout), // output [31 : 0] dout
.full(fifofull2), // output full
.empty(fifoem) // output empty
);
//FrontPanel endpoint instantiations
okBTPipeIn pipe80(
.okHE(okHE),
.okEH(okEHx[0*65 +: 65]),
.ep_addr(8'h80),
.ep_write(OKfifowrite),
.ep_dataout(OKdatain),
.ep_ready(~fifofull1)
);
okBTPipeOut pipeA0(
.okHE(okHE),
.okEH(okEHx[1*65 +: 65]),
.ep_addr(8'hA0),
.ep_read(OKfiforead),
.ep_datain(OKdataout),
.ep_ready(~fifoem)
);
And, Below is the python code.
dev = ok.okCFrontPanel()
dev.OpenBySerial("")
print(dev.IsFrontPanel3Supported())
// False
print(dev.IsHighSpeed())
// False
print(dev.IsFrontPanelEnabled())
// True
print(dev.WriteToBlockPipeIn(0xA0, 16, buf)) // buf = “\x00”*16
// 16
status = dev.ReadFromBlockPipeOut(0xA0, 16, buf)
print(status)
// Freezed
When I use this call ReadFromBlockPipeOut, the python is freezed. Any results don’t come out.
I don’t know if it’s a clock problem(clk_i is 80Mhz) in Verilog or a FIFO parameter problem.
I need your help.
Thank you.