Error in implement design


ERROR:NgdBuild:604 - logical block ‘ep20’ with type ‘okWireOut’ could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol ‘okWireOut’ is not supported in target

I am using ISE Design Suite 14.7 64-bit windows. And I tried to work with the VHDL and Verilog samples but encounted the above error with all the samples. This error also occurs with all the ‘ep’ series port mapping

Who can tell me whats going on…


Have you gone through the instructions on setting up a project that can be found in the README.txt in the samples folder? From that error it sounds like ISE is unable to find the ngc files necessary for the endpoints. They need to be placed in a directory that ISE searches, the project directory is generally a good place.


Thank you for answering my question! I have followed the README.txt and all the files including the ngc, ucf files are in the project directory. But this does not fix the problem. Currently I’m using ISE webpack 14.7, is the version a possible reason to cause this problem?


by the way, the VHDL sample I was running is the counter sample for XEM6010


ISE 14.7 should work fine for all samples on all of the current boards.

One thing that might be worth trying is adding the NGC files to your project if you haven’t already, the README.txt file states that you don’t need to do this but perhaps it will help ISE find them.

Can you also try re-creating the project over again? In the past users have had issues in which something was misconfigured, but trying again with all the steps in the correct order fixes the issue for them.


yes i added the ngc file to the project as well but it didn’t work. I plan to write simpler code to test it. By the way, the ISE design suit webpack doesnot include XC6SLX150 chip. there is only XC6SLX45 available. How do you fix it?


ISE requires a license to work with mid- to high-end parts, you’ll need to contact Xilinx for more information on how to get an ISE license as they have changed things with the move to Vivado.

If you’re using ngc files for the LX150 it may be that ISE refuses to read them in since they were generated for a part that it doesn’t support without a license. You could perhaps try generating a design for the LX45 part, you wont be able to test it without the right board but it should at least confirm if you are able to build the project.