Ep_write signal PipeIn

FrontPanel
#1

Hi,
I simulate the Front Panel Pipein and I realise that the ep_write signal from the pipe in remains activated for some time after its activation even if no signal comes out of the pipein. Do you know where this can come from?
It seems that the simulation doesn’t even really follow what I write in the tb for the signals in the pipein.

Thank you for your help !

#2

You forgot to post your code in the test bench.

#3

Here is the process I perform :

FrontPanelReset;
wait for 1ns;

-- Reset LFSR
SetWireInValue(x"00", x"0000_0001", NO_MASK);
UpdateWireIns;
SetWireInValue(x"00", x"0000_0000", NO_MASK);
UpdateWireIns;

wait for 10 ns;

pipeIn(0) := "00000000";
pipeIn(1) := "00001111";
pipeIn(2) := "00000000";
pipeIn(3) := "11110000";
WriteToPipeIn(x"80", pipeInSize);
wait for 10 ns;



pipeIn(4) := "11111111";
pipeIn(5) := "11111111";
pipeIn(6) := "11111111";
pipeIn(7) := "11111111";
WriteToPipeIn(x"80", pipeInSize);
wait for 10 ns;


pipeIn(4) := "11111111";
pipeIn(5) := "00000000";
pipeIn(6) := "00000000";
pipeIn(7) := "11111111";
WriteToPipeIn(x"80", pipeInSize);
wait for 10 ns;

end process;

This is after the OKHOSTCALLS I copied from the simulation example

#4

What do you have set for pipeInSize ?

1 Like
#5

The mistake was on the pipeInSize.

Thank you !