In my design I have some verilog modules that are “empty”, that is they contain only port declaration and no instances or assign statements. I want to keep them this way and change them later.
Is there any way to run complete synthesis and implementation with this kind of modules?
I declared them as black boxes in xcf file and that solved problem for synthesis, but the problem is translation process under implementation. I receive error message something like:
NgdBuild:604 - logical block … with type … could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol … is not supported in target ‘virtex5’.