Hi Jake,
I need a differential output and for instance, according to the Spartan datasheet, the pair I0_L20P_6 and IO_L20N_6, which are respectively P44 and P45, correspond to the XEM3001 JP2 pin 40 and 43.
Is this correct and if yes, is there somewhere an example showing the code to generate a differential output signal ?
Many thanks in advance.
Best regards,
Patrick.
Yes, you’ve got the pins correct. However, the Spartan-3 requires a 2.5v VCCO voltage for banks doing any of the supported differential standards. I’m not exactly sure what would happen if you used a 3.3v VCCO (which is what is provided by the XEM3001).
Refer to the various Xilinx docs to create constraints for the IOBs. You can do it in one of several ways depending on your preference. You can specify constraints within the UCF file (preferred) or Verilog. You can also use the Xilinx tools to configure IOB standards.
Jake
Xilinx does not recommend instantiating differential buffers in a 3.3V bank. I asked several folks at Xilinx and they said “don’t do it.” I didn’t try it for fear of damaging the part. (I have a feeling the part wouldn’t end up damaged due to some of the safeguards in the FPGA, but that’s just one non-Xilinx opinion.) We ended up building a daughter card to perform the differential output signals.
You can, however, receive LVDS or other differential standard in a 3.3V bank on your XEM.
What’s the meaning of ‘You can, however, receive LVDS or other differential standard in a 3.3V bank on your XEM.’ ? How to do that if the differential IO requires only 2.5V VCCO?
Is there any possiblity to rework to make all VCCO of FPGA set to 2.5V? That is, seperate the 3.3V power of FPGA from the other devices. Is there any schematic of the XEM3001 board?
Honda
Honda-
Driving the VCCO voltages on the XEM would be a difficult task because the 3.3v traces are very short and connected directly to the power plane (some are under the device on the top layer). If you’re particularly determined, you can get the specific pins from the Xilinx Spartan-3 datasheet, lift the pins, and connect them to a different voltage.
Of course, any warranty would be void at this point due to heavy modifications to the FPGA device and PCB.
Thank you. So you mean that the only solution for differential IO is to create a daughter board, right?
Do you have any example for BufferedPipes? My question is, how to check the FIFO status from host site?
Honda
Honda-
The easiest way to check the FIFO status is to send it back through a WireOut or PipeOut.
We have an update to the PipeTest sample which includes some testing for the BufferedPipes. This will be included in the next software release.
— Begin quote from lookyd
Xilinx does not recommend instantiating differential buffers in a 3.3V bank. I asked several folks at Xilinx and they said “don’t do it.” I didn’t try it for fear of damaging the part. (I have a feeling the part wouldn’t end up damaged due to some of the safeguards in the FPGA, but that’s just one non-Xilinx opinion.) We ended up building a daughter card to perform the differential output signals.
— End quote
For infos, I gave a try with 3.3V anyway and it seemed okay (I built the module described in the Apogee Application Note
http://www.apogeeddx.com/AN-03.pdf
to make the measurements).
Patrick.
That’s interesting… For further info, we have a new device that should be coming in the next couple months. It will have provisions for LVDS signals and user-provided bank voltages.
It will have high-density connectors for the I/Os and be based on the 1M or 1.5M gate Spartan-3.
More info will be posted here as it becomes available.
[QUOTE=Opal Kelly Support]That’s interesting… For further info, we have a new device that should be coming in the next couple months. It will have provisions for LVDS signals and user-provided bank voltages.
It will have high-density connectors for the I/Os and be based on the 1M or 1.5M gate Spartan-3.
More info will be posted here as it becomes available.[/QUOTE]
Mouth-watering and very exciting stuff…
Patrick.
In order to keep this information complete, there is a useful Xilinx answer record about this topic:
It seems that the LVDS inputs are powered by 2.5v VCCAUX and therefore do not depend on the bank voltage VCCO.
This is also useful for the XEM3010 because the differential clock inputs are on a bank which is hardwired (on the PCB) to 3.3v.
Yeah, I did the differential I/O with no problem, just use the right pins, and get the I/O buff from the language templates to do the translation…
Bill