I have very basic question regarding capability of XEM3005. I plan to use it for data acquisition of my DUT. My DUT streams out data at a rate defined by a data clock that the DUT also sends out. The data clock pattern is a square pulse train with a very low pulse width (~20us) and pulse spacing (~40us), however, the data clock can be off for a unknown period of time (say ~1ms). So the data clock and the data do not have a constant rate. As I understand (and verified), I can use the BRAM on the FPGA to acquired these data without any trouble. If I want take more than 10MB data, I need to use the SDRAM. Is there a problem if I stream these data into the 32MiB SDRAM at the data rate defined by the data clock? You answer is much appreciated.
Many, many thanks.