All current boards use the FX2LP (low-power) CY7C68013A.
You don’t actually perform any programming for the FX2. We have an on-board, upgradeable EEPROM which boots the Cypress device and handles all communications between the FPGA and PLL to the PC through USB.
You must embed Opal Kelly HDL modules (okWireIn, okPipeIn, okTriggerOut, etc.) into your FPGA design as necessary. FIFO’s are best implemented with okBufferedPipe modules, or, even better, with a Xilinx FIFO Core (now free) and okPipe module - this work seamlessly. All of these modules communicate with one “master” HDL block call okHostInterface, which is the control system between the FPGA and the FX2. The connection signals you listed are used by okHostInterface to communicate with the FX2. You don’t need to worry about them. okHostInterface and the other Opal Kelly HDL modules use the “ti” control lines to then inter-communicate.
On the PC side, you need to design your software with an Opal Kelly FrontPanel library which, through particular function calls, sends your data through USB to the correct HDL module in your FPGA in the proper format.
For instance, on the PC, you would call a member function like:
m_xem->WriteToPipeIn(0x80, data_length, data);
Which would stream an array (data) of length data_length to an Opal Kelly HDL module names okPipeIn which was setup with an endpoint address of 0x80 in your FPGA. Your FPGA design can feed this data directly into a FIFO, or do whatever with it.
I hope this helps a bit.