hello,
i am wondering, if you are using the CY68013, or the CY7C68013A, and how it is connected to the FPGA.
at cypress, i cant find a datasheet for the CY68103…
i need to know how the coummunication is handled (fifo/bus), to connect my IP-cores… the only thing in your manual to find about this, is that there are 4adrr,16data,cs,rdwr,int,busy signals…
do i need to use your firmware?
is it possiple to programm the Cypresschip?
wich HS-transfer-modes are supported?
thank you very much
best regards
Suheel
Suheel,
All current boards use the FX2LP (low-power) CY7C68013A.
[URL=“http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=14&rpn=CY7C68013A”]http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=14&rpn=CY7C68013A[/URL]
You don’t actually perform any programming for the FX2. We have an on-board, upgradeable EEPROM which boots the Cypress device and handles all communications between the FPGA and PLL to the PC through USB.
You must embed Opal Kelly HDL modules (okWireIn, okPipeIn, okTriggerOut, etc.) into your FPGA design as necessary. FIFO’s are best implemented with okBufferedPipe modules, or, even better, with a Xilinx FIFO Core (now free) and okPipe module - this work seamlessly. All of these modules communicate with one “master” HDL block call okHostInterface, which is the control system between the FPGA and the FX2. The connection signals you listed are used by okHostInterface to communicate with the FX2. You don’t need to worry about them. okHostInterface and the other Opal Kelly HDL modules use the “ti” control lines to then inter-communicate.
On the PC side, you need to design your software with an Opal Kelly FrontPanel library which, through particular function calls, sends your data through USB to the correct HDL module in your FPGA in the proper format.
For instance, on the PC, you would call a member function like:
m_xem->WriteToPipeIn(0x80, data_length, data);
Which would stream an array (data) of length data_length to an Opal Kelly HDL module names okPipeIn which was setup with an endpoint address of 0x80 in your FPGA. Your FPGA design can feed this data directly into a FIFO, or do whatever with it.
I hope this helps a bit.
Garrick
hi,
no sorry, it doesn’t help very much…
let me explain the requirements for our Product:
imagine a type of robot, there are sensors and actuators.
first, sensordata have to be transmitted to the PC,
there, some calculations are done, and according to these, data for the actuators have to be send to the robot.
for all these steps, the maximum time available, is 1ms.
this timing must not be violated.
the calculations take 0.5ms.
sensordata are just 40bytes, actuatordata are 6000bytes.
i think, to achieve these requierements, we will need to use a RTOS, like RTAI-linux (or can you tell me a Win-based RTOS), and we will have to use USB2.0 HighSpeed-Isochronous Data transfer, or some kind of microframe-bulk-transfer.
am i right? do you think your board is able to do this?
what would you recommend?
best Regards
Suheel
Our boards do not support isochronous data transfers, just bulk transfers.
I personally haven’t performed any performance calculations regarding data turn-around speeds, but I don’t think a board like this would be a good fit for your application as you’ve described it.
However, you might want to consider, if you application allows it, embedding a microcontroller into the FPGA and offloading some of your control algorithm to this processor. You can even run an RTOS on the microcontroller in the FPGA.
Opal Kelly should be releasing a sample peripheral soon for Xilinx’s MicroBlaze that will show how to easily communicate between an embedded FPGA microcontroller and a PC using the standard Opal Kelly HDL modules.
Garrick