Creating a forum to discuss Vivado/AXI with OK HDL endpoint development



I’d like to propose starting a forum thread that focuses and shares any development and ideas around coding, development within the Xilinx Vivado suite as well as interfacing OpalKelley HDL endpoints to the FPGA 7 series AXI system.



I think you just did. :slight_smile:



I think what I’m asking for is a ‘category’ tag. The whole toolchain methodology changes with Vivado and the 7 series chipsets.



Gotcha. We’ve created a new Xilinx 7-Series category.


Thanks… Heading over there.