Hey,
im trying to save the values of a counter in a textfile. Using verilog and the frontpanel.
Do i have to write the values in a ram or can i send them directly to the pc?
here is some code:
assign epA0wire = count; // Count is my reg for the counter
okPipeOut epA0(.ok1(ok1), .ok2(ok2x 17*0 +: 17 ]), .ep_addr(8’ha0), .ep_datain(epA0wire));
but it dont work. it writes something in the file, but it looks like random chars of the ascii table.
What clock is your counter on? The okPipeOut will read on the TI_CLK. Why aren’t you wiring up the EP_READ signal of okPipeOut?
okPipeOut epA0(.ok1(ok1), .ok2(ok2x 17*0 +: 17 ]), .ep_addr(8’ha0), .ep_datain(epA0wire), .ep_read(writeBit);
i got an 48MHz clk and an counter who set the bit for counting. its similarly to the counter example in frontpanel.
the problem is that if writeBit is 1, it writes too much values. how can i realize that it just write 1 value?
i got another question. it seems so that ep_datain writes the value of the ascii table. i tried out the new line (in ascii 10 or 13), but it writes tabs and no new line. it is possible to write a new line ?
EP_READ is an output from okPipeOut. See the FrontPanel User’s Manual and our examples for how to apply this.
You can’t “write too much” to an okPipeOut because you don’t actually write anything to it. okPipeOut reads from you.
As far as ASCII values go, pipes work with 8-bit values (on the PC side) – integers from 0…255 – with blatant disregard for how that underlying data is interpreted. If you want a 10, provide a 10. If you want a 13, provide a 13.