Counter Sample Simulation

I’m trying to get the Counters sample project up and simulating in ModelSim XE 6.3c.

I have done the following:

  • Created a new VHDL project in Xilinx Project Navigator v10.1.03
  • Copied okLibrary.vhd, Counters.vhd & xem3010.ucf from the Samples dir to the project dir
  • Created Counters_tb.vhd from dut_tf.vhd in the Simulation dir
  • Created a local modelsim.ini file which links to the okFPsim
  • Created a DO script file for loading the project in ModelSim

The contents of

vlib work
vcom -explicit  -93 "okLibrary_sim.vhd"
vcom -explicit  -93 "Counters.vhd"
vcom -explicit  -93 "Counters_tb.vhd"
vsim -L okFPsim  -t 1ps  Counters_tb
view wave
run 8 ms

When I init this project in ModelSim, I see the okFPsim and okFPsim_ver libraries loaded in the workspace, but get the following error (some of the compiling script has been truncated for brevity):

# -- Compiling entity counters_tb
# -- Compiling architecture sim of counters_tb
# vsim -L okFPsim -t 1ps Counters_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading std.textio(body)
# Loading ieee.std_logic_textio(body)
# Loading work.counters_tb(sim)
# Loading synopsys.attributes
# Loading ieee.std_logic_misc(body)
# Loading work.frontpanel
# Loading work.counters(arch)
# Loading unisim.vcomponents
# Loading work.okhost(archhost)
# Loading unisim.bufgdll(bufgdll_v)
# Loading unisim.ibufg(ibufg_v)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.clkdll(clkdll_v)
# Loading unisim.clkdll_maximum_period_check(clkdll_maximum_period_check_v)
# Loading unisim.bufg(bufg_v)
# Loading unisim.iobuf(iobuf_v)
# Loading unisim.obuf(obuf_v)
# ** Error: (vsim-3173) Entity 'C:\XEM\Counter\work.okcore' has no architecture.
# Load interrupted
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./ PAUSED at line 8

I have verified that all the ok*.ngc files are located in the root directly of the project (with the HDL files). Any ideas on why this won’t compile out of the box?

Many thanks.

After a long night, I found the source of the problem. The issue is that the okLibrary.vhd and okLibrary_sim.vhd files both compile to the same library location (both have a FRONTPANEL package). A more detailed description is below along with the workaround.

When I followed the instructions in the README.txt file in the .\Opal Kelly\FrontPanel\Samples\ directory, I added the okLibrary.vhd file to my project. That’s all fine and good, but I allowed Xilinx to generate a automatic DO script for running the simulation in ModelSim. Xilinx naturally compiles all design files included in the project, including okLibrary.vhd.

When I ran this script, ModelSim compiled the okLibrary components into the .\work\frontpanel\ directorie. But even after I replaced the “vcom okLibrary.vhd” line with “vcom okLibrary_sim.vhd” in the DO file, ModelSim assumed that the component compilations were current and didn’t refresh them. That led to the error listed in the original post.

The only way I found to fix this issue once okLibrary has been compiled into the workspace is to delete the entire workspace folder (located at .\work* if using the “vlib work” command) and recompile. I failed to get either the -refresh or -force_refresh command switches to fix the issue.

Opal Kelly — Is there any way that this can be avoided in future releases by either manipulating the okLibrary_sim package or combining the files? This seems like an easy problem to run into, especially for inexperienced users.

@alivingstone-- We don’t recommend using the Xilinx tools to launch ModelSim (in fact, we don’t recommend usage of the Xilinx GUI at all, but that’s another story).

It is much easier, more direct, and more efficient to author your own DO files. It also makes for better revision control capability, and faster iteration on HDL/simulation edits and runs.

— Begin quote from ____

We don’t recommend using the Xilinx tools to launch ModelSim

— End quote

I typically use the Xilinx tools to generate a skeleton DO file which I modify and make my own. Doing it this way normally ensures I get the compile order correct and the vcom/vsim syntax right the first time.

Regardless, the question still stands about the future combination of the okLibrary and okLibrary_sim files. This seems like a potential pitfall for users if the compilation of one locks down the simulation workspace.