Cotrol sample rebuild problem


I created a new project for control sample verilog file. and generated the bit file sucessfully with all default setting (ISE9.2i). I ran the FrontPanel, download the bit file for my xem3001v2 board. load the tester.xfp. But the software doesn’t run. If I download the original bit file, and it runs. So is there anything I missed or is there any sequence I should follow?


Tony Hu

My guess here is that you did not include the UCF file in your project, so the Xilinx ISE software just assigned the FPGA pins as it saw fit with no regard to the actual PCB design.