Compiling PipeTest vhdl


#1

Hi,

I have a problem compiling the vhdl code for the PipeTest. The sythesis process fails. This is the log:

Release 7.1.01i - xst H.39
Copyright © 1995-2005 Xilinx, Inc. All rights reserved.
–> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.33 s | Elapsed : 0.00 / 1.00 s

–> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.33 s | Elapsed : 0.00 / 1.00 s

–> Reading design: okbufferedpipein.prj

TABLE OF CONTENTS

  1. Synthesis Options Summary
  2. HDL Compilation
  3. HDL Analysis
  4. HDL Synthesis
  5. Advanced HDL Synthesis
    5.1) HDL Synthesis Report
  6. Low Level Synthesis
  7. Final Report
    7.1) Device utilization summary
    7.2) TIMING REPORT

=========================================================================

  •                  Synthesis Options Summary                        *
    

=========================================================================
---- Source Parameters
Input File Name : “okbufferedpipein.prj”
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name : “okbufferedpipein”
Output Format : NGC
Target Device : xc3s400-4-pq208

---- Source Options
Top Module Name : okbufferedpipein
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Equivalent register Removal : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto

---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
Write Timing Constraints : NO
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5

---- Other Options
lso : okbufferedpipein.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
enable_auto_floorplanning : No

=========================================================================

=========================================================================

  •                      HDL Compilation                              *
    

=========================================================================
Compiling vhdl file “Z:/dataDisk/Opal Kelly/FrontPanel/XEM3001v2/Samples/PipeTest_custom1/vhdl/…/…/…/Xilinx/okLibrary.vhd” in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
Entity compiled.
FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13.276.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at
http://support.xilinx.com
. If you need further assistance, please open a Webcase by clicking on the “WebCase” link at
http://support.xilinx.com

Has anybody got an idea?

Thanks a lot.

Cheers, Christian


#2

This looks to me like you’re not doing synthesis on ‘toplevel.vhd’ but rather on the okbufferedpipein.

Select “toplevel.vhd” in the project navigator and run synthesis on that.

Jake