From the documentation:
EP_CLK - Input - Endpoint clock.
Because the FIFO is asynchronous, the two ports can run with
different clocks (TI_CLK for the target interface side and EP_CLK for the user-logic side).
EP_WRITE - Input - When asserted, writes the data on EP_DATAIN to
the FIFO and advances the write pointer to the next
Now, from this information I gather that the FIFO will latch the data on EP_DATAIN[15:0] at the next EP_CLK after EP_WRITE goes high.
My question is, how many clocks per data is needed?
Perhaps it only needs one and it is possible to latch new data on every clock cycle? (assuming that it is not full)
Also, does it latch on the rising or falling edge of the clock?
Or does the clock play no part in the latching of the data?
If it is the clock that latches the data, how much set up time is needed on EP_DATAIN[15:0] and EP_WRITE before you clock in the data?
It would be useful to have a timing diagram noting set up times and hold times as well as which signal edge actually latches the data into the FIFO…
As it stands, the documentation seems a little ambiguous.
Thanks for your attention. I think this module is great!