Can't Blink an LED on the XEM7310MT-A200 board

I am trying to blink an LED on a new XEM7310MT-A200 board that I just bought. In order to blink the LED I am using a clock divider circuit that converts a 200MHz clock to a 1Hz signal using a counter that counts up to 99999999 which then inverts a register which is assigned to my LED. This causes the LED to be on for 0.5 seconds and off for 0.5 seconds.

My code is running fine in simulations but when I load the bitstream to the board using FrontPanel, all the LEDs remain on while the LED that I assigned to the 1Hz signal is noticeably brighter than the rest. I am wondering if I assigned the pins incorrectly or have another I/O setting that is wrong.

When I assigned my pins I downloaded the XEM7310MT constraints file from Opal Kelly’s website and only uncommented the following lines:
create_clock -period 5.000 -name sys_clk [get_ports clk]
set_property PACKAGE_PIN A13 [get_ports divided_clk]
set_property IOSTANDARD LVCMOS15 [get_ports divided_clk]

The first line was used to assign the system clock to the input port “clk” in my module. The second line was “led0” that was assigned to the output of my module which uses the variable “divided_clk” while the last line set the led voltage to 1.5V.

I also defined the input clock as a LVCMOS25 signal and the output divided clock (assigned to the LED) as a LVCMOS15 signal in Vivado. Something I noticed was Vivado assigned pin U20 to my clk input and pin A13 to my output divided clock. Neither of these pins are defined on the XEM7310MT pin reference which I believe is part of the problem (I would attach an image but new users aren’t allowed).

I have been troubleshooting this for hours and I can’t find my issue. This is my first time using an external constraints file so any feedback on what I did wrong would be greatly appreciated.

Does anything here help?

Have you looked at the source HDL for the Counters sample?

Yes I did see this so I now know my LED pin is assigned correctly. Could you tell me why the constraints file is choosing pin U20 for my clock not W11? I read on your clock oscillator page that I need to set DIFF_TERM=FALSE which I am not sure how to do.

Could you also confirm that the three constraints I am using are correct? I am not sure if I need to set the IO standard for the divided clock.

Okay I got the LED to blink once I changed my divided clock signal to switch between 0 and high Z. The issue I am having now is the LED I assigned to my divided clock is blinking fine but the other 7 LEDs are dimly lit when they should be turned off since I do not even have their pins assigned to anything.

Does anyone have experience with this issue or know what could be causing it?

You should assign the remaining LED pins to FPGA I/O and set those pins to high-Z.

In case anyone else runs into this issue the easier way to solve this is by right clicking on “Generating Bitstream” in Vivado > Go to Bitstream Settings > Click “Configure additional bitstream settings” > Under the Configuration Tab go down to the “Configuration Pin Settings during User Mode” > Set Unused IOB Pins to “PULLNONE”. Then regenerate your bitstream and only the LEDs you have assigned in your constraints file will be used