I’m trying to build the example code for the PipeTest using the latest FrontPanel (4.0.2) for the Opal Kelly XEM6110 PCI-e. I generated the ISE VHDL project using ISE 12.4 by following the directions here: http://forums.opalkelly.com/showthread.php?298-Setting-up-Xilinx-ISE-Projects. Unfortunately, the mapping phase fails. I’ve attached the log file with this post.
I successfully built the example code with FrontPanel 4.0.0, but was unable to connect to the device with the provided software, with the “IsFrontPanelEnabled()” method returning false. Using your pre-compiled bit file and .exe, this command succeeded.
Solving either one of these problems would be fine! Thanks!
Any help would be greatly appreciated.
pipetest.zip (5.1 KB)