Cannot generate programming file with FP 4.0.2

I’m trying to build the example code for the PipeTest using the latest FrontPanel (4.0.2) for the Opal Kelly XEM6110 PCI-e. I generated the ISE VHDL project using ISE 12.4 by following the directions here: http://forums.opalkelly.com/showthread.php?298-Setting-up-Xilinx-ISE-Projects. Unfortunately, the mapping phase fails. I’ve attached the log file with this post.

I successfully built the example code with FrontPanel 4.0.0, but was unable to connect to the device with the provided software, with the “IsFrontPanelEnabled()” method returning false. Using your pre-compiled bit file and .exe, this command succeeded.

Solving either one of these problems would be fine! Thanks!

Any help would be greatly appreciated.


pipetest.zip (5.1 KB)

There was a small change that hadn’t made it’s way to the VHDL version of okLibrary in the last release. I’m attaching an updated version. Please give it a try and let us know if it takes care of the issues you are seeing. VHDL samples first & counters built (ISE12.3) and ran fine here on the test station. Sorry for the hassle.

Cheers,
Opal Kelly Support

[ATTACH]213[/ATTACH]


okLibrary_vhd.zip (3177 Bytes)

I’ve also experienced mapping errors with the version of okLibrary.vhd that was supplied with the XEM6110 board only a couple of weeks ago. Could you please ensure that updated files are supplied with the XEM6110 in the future.